Abstract: An integrated circuit device includes first and second stack structures and a side connection structure. The first stack structure includes a first transistor and a second transistor stacked thereon. The second stack structure includes a third transistor and a fourth transistor stacked thereon. Each of the first to fourth transistors includes an active layer having a channel region and a source/drain region, a gate structure wrapping around the channel region, and a source/drain contact surrounding the source/drain region. The active layer and the side connection structure extend substantially along a first direction in a top view, and the gate structure extends substantially along a second direction orthogonal to the first direction in the top view. The side connection structure electrically connects one of the source/drain contact and the gate structure of the first transistor to one of the source/drain contact and the gate structure of the third transistor.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a gate structure, and a gate isolation. The first transistor is of a first conductivity type and comprises a first active region structure. The second transistor is of a second conductivity type different from the first conductivity type and comprises a second active region structure. The second transistor is disposed above the first transistor. The gate structure comprises a first gate connection contacting the first active region structure and a second gate connection contacting the second active region structure. The gate isolation is disposed between the first gate connection and the second gate connection.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a cell. The cell includes a gate structure, a first active region, a second active region, a first signal line, and a second signal line. The gate structure extends along a first direction. The first active region extends along a second direction different from the first direction and intersects the gate structure. The second active region extends along the second direction and intersects the gate structure. The first active region overlaps the second active region along a third direction different from the first direction and the second direction. The first signal line is over the first active region and configured to transmit an input signal. The second signal line is under the second active region and configured to transmit an output signal.

Abstract: A cell region (of a device) includes: a first active region (AR); first MD structures aligning to beta tracks; and in a first metallization layer, segments aligning to alpha tracks. For one or more first or second locations, a corresponding region of the first AR is configurable as a source region or a drain region. For one or more third locations, a corresponding region of the first AR is configurable as a source region, but not as a drain region. For one or more fourth locations, a corresponding region of the AR is not configurable as a source region or a drain region. Each of the first to fourth locations is at an intersection of a corresponding alpha track and a corresponding beta track.

Abstract: An integrated circuit includes a first and second active region, a first and second contact, a first conductor and a first insulating region. The first active region extends in a first direction, is on a first level above a front-side of a substrate, and corresponds to a first set of transistors. The second active region extends in the first direction, is on a second level, and corresponds to a second set of transistors. The first contact extends in a second direction, is on a third level, and overlaps the first active region. The second contact extends in the second direction, is on a fourth level, overlaps the second active region. The first conductor extends in the first direction, is on the third level and the fourth level, and is coupled to the first contact and the second contact. The first insulating region is within a recess of the first conductor.

Abstract: An embodiment semiconductor structure includes a first active region and a second active region extending along a first direction, a functional gate structure and a non-functional gate structure aligned with each other and extending along a second direction, and a metallization layer over the functional gate structure and the non-functional gate structure. The metallization layer defines a first metallization region, a second metallization region, and one or two middle metallization regions between the first metallization region and the second metallization region. The functional gate structure overlaps the first metallization region and overlaps one of the one or two middle metallization regions to define an overlapped portion of the one of the one or two middle metallization regions. The overlapped portion has a space defined therein sized for a connection feature between the functional gate structure and the one of the one or two middle metallization regions.

Abstract: An integrated circuit includes a plurality of cells abutted to one another, each of the plurality of cells corresponding to a respective circuit component. Each of the plurality of cells includes: a plurality of active regions extending along a first lateral direction; a plurality of gate structures extending along a second lateral direction perpendicular to the first lateral direction and traversing one or more of the plurality of active regions; a plurality of first interconnect structures extending along the first lateral direction and vertically disposed above the plurality of gate structure; and a plurality of second interconnect structures extending along the second lateral direction and vertically disposed above the plurality of first interconnect structures. Each of the plurality of second interconnect structures is shifted from a corresponding one of the plurality of gate structures with a distance along the first lateral direction.

Abstract: An IC device includes first and second bit circuits adjacent to each other along a row direction, third and fourth bit circuits adjacent to each other along the row direction, and a first column of output pins aligned in a column direction. The first and second bit circuits include first through fourth power rails and first through sixth active areas extending in the row direction, and the third and fourth bit circuits include the fourth power rail, fifth through seventh power rails, and seventh through twelfth active areas extending in the row direction. The first column of output pins includes first and second output pins adjacent to the second bit circuit and coupled to the respective first and second bit circuits and third and fourth output pins adjacent to the fourth bit circuit and coupled to the respective third and fourth bit circuits.