Patents by Inventor Chen-Lun Lin
Chen-Lun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936418Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.Type: GrantFiled: April 27, 2021Date of Patent: March 19, 2024Assignee: KAIKUTEK INC.Inventors: Mike Chun-Hung Wang, Chun-Hsuan Kuo, Mohammad Athar Khalil, Wen-Sheng Cheng, Chen-Lun Lin, Chin-Wei Kuo, Ming Wei Kung, Khoi Duc Le
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Publication number: 20220345173Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.Type: ApplicationFiled: April 27, 2021Publication date: October 27, 2022Applicant: KaiKuTek Inc.Inventors: Mike Chun-Hung WANG, Chun-Hsuan KUO, Mohammad Athar KHALIL, Wen-Sheng CHENG, Chen-Lun LIN, Chin-Wei KUO, Ming Wei KUNG, Khoi Duc LE
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Patent number: 11444573Abstract: The invention discloses an oscillator, including a voltage switching circuit, a voltage adjustment circuit and a frequency generation circuit. The voltage switching circuit receives an output voltage signal whereby the output voltage signal switches a first input voltage signal to a first voltage level signal and switches a second input voltage signal to a second voltage level signal. The voltage adjustment circuit receives the first voltage level signal and the second voltage level signal, whereby the first voltage level signal and the second voltage level signal generate the first adjustment voltage signal and the second adjustment voltage signal. The frequency generation circuit is connected to the voltage adjustment circuit, and receives the first adjustment voltage signal and the second adjustment voltage signal to generate the first output frequency signal and the second output frequency signal according to the first adjustment voltage signal and the second adjustment voltage signal.Type: GrantFiled: September 17, 2021Date of Patent: September 13, 2022Assignee: KaiKuTek Inc.Inventors: Mike Chun-Hung Wang, Chen-Lun Lin, Guan-Sian Wu, Chin-Wei Kuo, Ming Wei Kung, Wen-Sheng Cheng, Chun-Hsuan Kuo
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Patent number: 10771070Abstract: A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation.Type: GrantFiled: September 28, 2018Date of Patent: September 8, 2020Assignee: KAIKUTEK INC.Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun-Hung Wang
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Patent number: 10707879Abstract: A frequency-modulated continuous-wave radar system includes a waveform generator, a delta-sigma modulation circuit, a voltage controlled oscillator, a frequency divider circuit, a control circuit, an injection locked oscillator, a power amplifier circuit, a first power detection circuit, a second power detection circuit, a third power detection circuit, and a calibration engine circuit. The waveform generator, the delta-sigma modulation circuit, the voltage controlled oscillator, the frequency divider circuit, and the control circuit form a phase locked loop.Type: GrantFiled: July 9, 2018Date of Patent: July 7, 2020Assignee: KaiKuTek INC.Inventors: Mike Chun Hung Wang, Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang
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Patent number: 10536152Abstract: An oscillating circuit has an injection-locked oscillator (ILO) and a calibration circuit. The ILO has a Gm cell and an LC tank. A first node of the Gm cell receives a first injection signal, and a second node of the Gm cell receives a second injection signal. The first injection signal and the second injection signal are differential signals. The Gm cell provides a negative resistance between a first output end and a second output end of the Gm cell. When the calibration circuit tunes a resonant frequency of the LC tank of the ILO, the magnitude of the negative resistance is reduced to control the ILO to stop self-oscillating. After finishing tuning the resonant frequency of the LC tank, the calibration circuit controls the ILO to start self-oscillating by increasing the magnitude of the negative resistance.Type: GrantFiled: October 21, 2018Date of Patent: January 14, 2020Assignee: KaiKuTek INC.Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun Hung Wang
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Patent number: 10498294Abstract: A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.Type: GrantFiled: August 21, 2018Date of Patent: December 3, 2019Assignee: KaiKuTek INC.Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun Hung Wang
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Publication number: 20190319630Abstract: A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.Type: ApplicationFiled: October 3, 2018Publication date: October 17, 2019Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun-Hung Wang
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Publication number: 20190319589Abstract: A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.Type: ApplicationFiled: August 21, 2018Publication date: October 17, 2019Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun Hung Wang
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Publication number: 20190319596Abstract: A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation.Type: ApplicationFiled: September 28, 2018Publication date: October 17, 2019Inventors: Pang-Ning CHEN, Chen-Lun LIN, Ying-Chia CHEN, Wei-Jyun WANG, Mike Chun-Hung WANG
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Publication number: 20190317189Abstract: A frequency-modulated continuous-wave radar system includes a waveform generator, a delta-sigma modulation circuit, a voltage controlled oscillator, a frequency divider circuit, a control circuit, an injection locked oscillator, a power amplifier circuit, a first power detection circuit, a second power detection circuit, a third power detection circuit, and a calibration engine circuit. The waveform generator, the delta-sigma modulation circuit, the voltage controlled oscillator, the frequency divider circuit, and the control circuit form a phase locked loop.Type: ApplicationFiled: July 9, 2018Publication date: October 17, 2019Inventors: Mike Chun Hung Wang, Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang
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Publication number: 20190319581Abstract: An oscillating circuit has an injection-locked oscillator (ILO) and a calibration circuit. The ILO has a Gm cell and an LC tank. A first node of the Gm cell receives a first injection signal, and a second node of the Gm cell receives a second injection signal. The first injection signal and the second injection signal are differential signals. The Gm cell provides a negative resistance between a first output end and a second output end of the Gm cell. When the calibration circuit tunes a resonant frequency of the LC tank of the ILO, the magnitude of the negative resistance is reduced to control the ILO to stop self-oscillating. After finishing tuning the resonant frequency of the LC tank, the calibration circuit controls the ILO to start self-oscillating by increasing the magnitude of the negative resistance.Type: ApplicationFiled: October 21, 2018Publication date: October 17, 2019Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun Hung Wang
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Patent number: 10425086Abstract: A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.Type: GrantFiled: October 3, 2018Date of Patent: September 24, 2019Assignee: KaiKuTek Inc.Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun-Hung Wang
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Publication number: 20180128647Abstract: A measuring device is provided for determining the position of a susceptor in a reactor housing. The measuring device includes a central element, which can be fastened on the susceptor at a predefined location, and a plurality of sensing arms, which protrude from the central element beyond an outer periphery of the susceptor. The sensing arms respectively include a sensing section that can be brought in touching contact with a contact zone. The contact zone is formed by an inner periphery of the reactor housing or a component arranged in the reactor housing. Using the measuring device, the position of a susceptor of a CVD reactor is determined relative to the reactor housing or a component arranged in the reactor housing.Type: ApplicationFiled: November 10, 2016Publication date: May 10, 2018Inventors: Gi Youl Kim, Mark Chen-Lun Lin, Gregory Siu, Ki Chul Park, Jonathan David Mohn, H. William Luca, JR.