Patents by Inventor Chen-Lun TING

Chen-Lun TING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268193
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes disposing a mandrel layer on a dielectric layer and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nm. The method also includes etching the dielectric layer by using the first spacer, the second spacer, the third spacer, and the fourth spacer as etching masks to form a first dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element. The method also includes forming a first shielding line between the second dielectric element and the third dielectric element.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: CHEN-LUN TING, TSENG-FU LU, YUNG-CHIH YANG
  • Publication number: 20230268287
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface, a first signal line disposed on the surface of the substrate, and a second signal line disposed on the surface of the substrate and spaced apart from the first signal line. The semiconductor device also includes a first shielding line between the first signal line and the second signal line. The minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: CHEN-LUN TING, TSENG-FU LU, YUNG-CHIH YANG
  • Patent number: 10763212
    Abstract: A semiconductor structure includes a substrate including a surface, a first doped region and a second doped region, wherein the first doped region and the second doped region are disposed under the surface; a gate structure disposed between the first doped region and the second doped region; a capacitor disposed over and electrically connected to the first doped region; and a bit line disposed over and electrically connected to the second doped region, wherein the bit line includes a conductive portion and an insulating portion surrounding the conductive portion, and the insulating portion includes ferroelectric material.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Cheng-Hsien Hsieh, Ching-Chia Huang, Chen-Lun Ting, Tseng-Fu Lu, Wei-Ming Liao
  • Publication number: 20200176452
    Abstract: A memory device includes a substrate, a first gate structure, and a first oxide layer. The substrate has a first protruding portion and a second protruding portion adjacent to the first protruding portion. The first gate structure is on the substrate and between the first and second protruding portions. The first oxide layer is disposed between the substrate and the first gate structure, and includes a first portion and a second portion. The first portion is between the first gate structure and the first protruding portion, the second portion is between the first gate structure and the second protruding portion, and a thickness of the first portion is greater than a thickness of the second portion.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 4, 2020
    Inventors: Chen-Lun TING, Tseng-Fu LU, Wei-Chih WANG