Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.

Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device, a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.

Abstract: A cleaning container and method for using the same for chemically cleaning elongated members including quartz thermocouple sleeves including a first body member and a second body member said first body member and second body member respectively forming a first containing space and a second containing space including a first means for reversibly compressively sealing the first body member and the second body member to a form a combined containing space for sealably holding a cleaning solution level; a cap member disposed at a distal end of the first body member said cap member including a second means for reversibly compressively sealing a first opening in communication with the first containing space; and, a second opening centrally disposed in a distal end of the second containing space said second opening including a third means for reversibly compressively sealing around at least one elongated member penetrating through said second opening.

Abstract: A cleaning container and method for using the same for chemically cleaning elongated members including quartz thermocouple sleeves including a first body member and a second body member said first body member and second body member respectively forming a first containing space and a second containing space including a first means for reversibly compressively sealing the first body member and the second body member to a form a combined containing space for sealably holding a cleaning solution level; a cap member disposed at a distal end of the first body member said cap member including a second means for reversibly compressively sealing a first opening in communication with the first containing space; and, a second opening centrally disposed in a distal end of the second containing space said second opening including a third means for reversibly compressively sealing around at least one elongated member penetrating through said second opening.

Abstract: An apparatus for fixing the position of a quartz furnace tube in a semiconductor processing furnace is described. The furnace is of the type that has a cylindrical body possessing an open end through which the tube may be withdrawn, and a base postioned on the open end, wherein the tube includes a flange portion secured to the base through which gas may be withdrawn from or introduced into the furnace tube. The tube is coaxially disposed within the furnace body. The apparatus may include two clamp halves each has a half-circular shape for engaging the flange portion of the furnace tube onto the base, and a mounting means for mounting the two clamp halves to the base.

Abstract: A pico fuse detector assembly incorporating a probe structure that minimizes short-out of closely adjacent pico fuses during testing has two probe arms, each pivotably connected at one end to a detector body with their free ends adjustably dispaceable from each other and respectively accomodating improved probe elements thereon. Each probe element has a conductive lead disposed inside an insulating housing connected at one end to a set of test contacts extending from the bottom of the housing. The other end of the lead is coupled by a spring to a test circuit. The restricting of the contact area with the isolating housing limits the chance of the contacts accidentally being placed at a location to cause damage to two closely arranged adjacent pico fuses under test and thus obviates the problem of fuse short-out during measuring of the closely arranged fuses. Also, the contacts and lead are axially movable by virtue of the spring-mounting to the test circuit.

Abstract: In a CVD vacuum chamber processing system for depositing a blanket of refractory material, such as tungsten, upon a frontside of a semiconductor wafer, an inert gas, such as argon is directed to the backside of the wafer in a manner so as to prevent the chamber reaction gases from reacting with polysilicon or other materials on the backside of the wafer as well as to prevent the deposition of the blanket material on the backside of the wafer. This method alleviates the problems of particulate generation and loss of wafer backside datum surface due to the inadvertent buildup of unwanted materials. The wafer is placed on a heater platen and is secured by a specified range of vacuum pressures. The wafer is exposed to specified ranges of chamber pressure during the deposition phase. During the purge phase, the chamber pressure is reduced and the wafer chucking pressure is increased to a specified range. The method is terminated with the equalization of pressure between the front and backside of the wafer.