Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: A bandgap circuit with adaptive start-up design is shown, which includes a bandgap core and a start-up circuit. The bandgap core uses paired bipolar transistors (BJTs) to eliminate temperature-sensitive factors and thereby generate a bandgap voltage that is independent of temperature variations. The start-up circuit couples an emitter terminal of a first BJT of the paired BJTs to a power line to start up the bandgap core. The start-up circuit includes a reference BJT that provides a threshold voltage as a reference for disconnecting the power line from the emitter terminal of the first BJT.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: A system includes an electronic display panel that has a plurality of pixels configured to depict frames of image data. The electronic display also includes display driver circuitry configured to, for a first frame of image data representing first image content, modify a gate-to-source voltage of a transistor of a first pixel of the plurality of pixels to a content-dependent first gate-to-source voltage. Additionally, after modifying the gate-to-source voltage to the first gate-to-source voltage, the display driver circuitry is configured to program the first pixel by modifying the gate-to-source voltage to a gate-to-source programming voltage that differs from the first gate-to-source voltage and is based on image data associated with the pixel from the first frame of the image data. Furthermore, the display driver circuitry is configured to cause the plurality of pixels to emit light.

Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to a drive transistor and other associated thin-film transistors. The array may be grouped into column pairs, where each column pair includes a first pixel column and a second pixel column that is mirrored with respect to the first pixel column. The drive transistors within each column pair may be formed towards the center of that column pair, whereas the data lines associated with that column pair may be formed along the outer peripheral edges of that column pair. Configured in this way, parasitic coupling between the data lines and any sensitive/floating nodes of the drive transistor may be substantially reduced, which mitigates pixel column crosstalk and ensures luminance uniformity across the display.

Abstract: A system includes an electronic display panel that has a plurality of pixels configured to depict frames of image data. The electronic display also includes display driver circuitry configured to, for a first frame of image data representing first image content, modify a gate-to-source voltage of a transistor of a first pixel of the plurality of pixels to a content-dependent first gate-to-source voltage. Additionally, after modifying the gate-to-source voltage to the first gate-to-source voltage, the display driver circuitry is configured to program the first pixel by modifying the gate-to-source voltage to a gate-to-source programming voltage that differs from the first gate-to-source voltage and is based on image data associated with the pixel from the first frame of the image data. Furthermore, the display driver circuitry is configured to cause the plurality of pixels to emit light.

Abstract: A computer stick docking system and a power management method thereof are provided. The computer stick docking system includes a docking station and a computer stick device. The docking station is configured to receive a display device and a computer stick device, including a docking battery and a docking HDMI interface circuit. The computer stick device includes a computer-stick controller and a computer-stick HDMI interface circuit. The computer-stick controller is configured to load an operating system. The computer-stick HDMI interface circuit, coupled to the computer-stick controller, is configured to request battery power information of the docking battery from the docking station after it is powered on and the computer-stick HDMI interface circuit is connected to the docking station.

Abstract: A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.

Abstract: A method for preparing a hepatocyte includes the following steps: providing a liver progenitor cell, proliferating the liver progenitor cell in a medium supplemented with nicotinamide, insulin-transferrin-selenium (ITS) and EGF, and inducing the liver progenitor cell into the hepatocyte having a hepatic cord-like structure morphology. In one embodiment, the method further includes providing a pluripotent stem cell and differentiating the pluripotent stem cell into the liver progenitor cell.

Abstract: A computer stick docking system and a power management method thereof are provided. The computer stick docking system includes a docking station and a computer stick device. The docking station is configured to receive a display device and a computer stick device, including a docking battery and a docking HDMI interface circuit. The computer stick device includes a computer-stick controller and a computer-stick HDMI interface circuit. The computer-stick controller is configured to load an operating system. The computer-stick HDMI interface circuit, coupled to the computer-stick controller, is configured to request battery power information of the docking battery from the docking station after it is powered on and the computer-stick HDMI interface circuit is connected to the docking station.

Abstract: A display includes a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each pixel includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The scan lines and the data lines are coupled to the pixels. Two color sub-pixels in the same row coupled to the same data line are coupled to different scan lines, and all of the second color sub-pixels in the same row are coupled to the same scan line.

Abstract: An Nth shift register unit includes an input circuit, a voltage regulator, and an output circuit. The input circuit is disposed to control a voltage at a control node of the Nth shift register unit according to a first scan signal of an (N?K)th shift register unit or a second scan signal of an (N+K)th shift register unit. The voltage regulator includes a first coupling element coupled to a first clock, a first switch disposed to receive the voltage at the control node and generate a reverse bias for reducing current leakage, and a switch control unit disposed to control the first switch according to the first clock. The output circuit is disposed to output a third scan signal.

Abstract: A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.

Abstract: Cultured hepatocytes with hepatic-cord structure and the applications were disclosed. Also the disclosure performed the method for obtaining the cultured hepatocytes with hepatic-cord structure from pluripotent stem cells and progenitor cells.