Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and an S/D contact structure formed adjacent to the gate structure. The FinFET device structure includes a protection layer formed on the S/D contact structure, and the protection layer has a convex top surface.

Abstract: A method includes providing a structure including a substrate and a fin-shaped structure protruding from the substrate, forming an isolation structure and a protecting layer thereon over the substrate and adjacent to a sidewall of the fin-shaped structure, growing a source/drain feature on a source/drain region of the fin-shaped structure, depositing a contact etch stop layer (CESL) over the source/drain feature, depositing a first interlayer dielectric (ILD) layer, a capping layer, and a second ILD layer over the CESL, forming a source/drain contact plug in the first ILD layer to electrically couple to the source/drain feature, forming a metal silicide layer between the source/drain feature and the source/drain contact plug, thinning down the substrate from a bottom of the structure, forming an opening exposing a bottom surface of the source/drain contact plug and a bottom surface of the protecting layer, and depositing a backside conductive feature in the opening.

Abstract: A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

Abstract: A method of fabricating a semiconductor device includes forming a first active region and a second active region over a substrate, depositing an isolation structure between the first and second active regions, forming a gate structure across the first active region and the second active region, forming a trench dividing the gate structure into a first segment and a second segment, depositing a dielectric feature in the trench, thinning the substrate and the isolation structure to expose a bottom surface of the dielectric feature, selectively removing a surface layer of the dielectric feature to form an air gap, and depositing a seal layer capping the air gap.

Abstract: A semiconductor structure according to the present disclosure includes a semiconductor structure including a backside dielectric layer, a backside etch stop layer (ESL) over the backside dielectric layer, a first source/drain feature and a second source/drain feature over the backside ESL and spaced apart from one another along a first direction, a frontside source/drain contact disposed over the first source/drain feature and the second source/drain feature, a backside contact feature through the backside dielectric layer and the backside ESL to couple to the first source/drain feature, a through via extending through the backside dielectric layer and the backside ESL, a base fin between the backside ESL and the second source/drain feature; and an isolation feature including a portion extending along sidewalls of the base fin. The backside contact feature interfaces the through via in the backside dielectric layer and the isolation feature includes an oxide-based material.

Abstract: A semiconductor device includes a substrate, first, second, and third fins protruding from the substrate, first, second and third source/drain (S/D) features over the first, second, and third fins, respectively, a first isolation feature over the substrate and disposed between the first and second S/D features, a second isolation feature over the substrate and disposed between the second and third S/D features, and a dielectric layer disposed on sidewalls of the first, second, and third S/D features and on sidewalls of the first and second isolation features. A top surface of the first isolation feature is above a top surface of the second isolation feature.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a first source/drain region, a second source/drain region disposed adjacent the first source/drain region, and a contact etch stop layer disposed over the first source/drain region. A top surface of the first source/drain region is covered by the contact etch stop layer. The structure further includes a first conductive feature disposed below the first and second source/drain regions, and the first conductive feature is electrically connected to the first and second source/drain regions.

Abstract: A method of the present disclosure includes forming a stack on a substrate, patterning the stack and the substrate to form first and second active regions, forming an isolation structure between the first and second active regions, depositing an isolation structure protecting layer on the isolation structure, forming a dummy gate stack across the first and second active regions, recessing the first and second active regions to form first and second trenches, forming first and second source/drain features in the first and second trenches, removing the dummy gate stack to form a gate trench, depositing a gate structure in the gate trench and interfacing the isolation structure protecting layer, thinning the substrate and the isolation structure, forming a backside opening exposing a bottom surface of the first source/drain feature, and forming a backside via in the backside opening and in electrical coupling with the first source/drain feature.

Abstract: A semiconductor structure includes an active region including a semiconductor fin base, a stack of nanostructures over the semiconductor fin base, and an epitaxial feature over the semiconductor fin base and connected to at least one of the nanostructures, the active region extending lengthwise in a first direction. The semiconductor structure further includes a gate structure wrapping around each of the nanostructures, the gate structure extending lengthwise in a second direction perpendicular to the first direction, and a backside butted contact disposed directly under and electrically connected to the epitaxial feature and the gate structure. A portion of the backside butted contact extends into the gate structure and the epitaxial feature.

Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

Abstract: A method includes forming a plurality of channel layers vertically stacked over a semiconductor substrate; forming a gate structure surrounding the channel layers; forming a first source/drain epitaxial structure on a first side of the channel layers; etching a first opening at least in the semiconductor substrate and the first source/drain epitaxial structure expose a backside of the first source/drain epitaxial structure; and forming an isolation plug in the first opening, wherein the isolation plug is at least laterally aligned with a bottommost one of the channel layers.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

Abstract: In an embodiment, an exemplary method includes receiving a structure comprising a fin-shaped active region protruding from a substrate and comprising a channel region and a source/drain region, and a dummy gate stack over the channel region. The method also includes recessing the source/drain region to form a source/drain trench, forming a dielectric layer over the substrate and in the source/drain trench, epitaxially forming a source/drain feature in the source/drain trench and over the dielectric layer, replacing the dummy gate stack with a gate structure, performing an etching process to etch the substrate and the dielectric layer to form an opening exposing a bottom surface of the source/drain feature, forming a dielectric liner extending along surfaces of the dielectric layer and the substrate exposed by the opening, and forming a conductive feature in the opening and under the source/drain feature.

Abstract: A semiconductor structure includes a substrate and nanostructures over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures. The gate structure comprises a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures. In addition, the semiconductor structure includes a contact etch stop layer over the source/drain feature. The contact etch stop layer is separated from the gate structure by an air spacer. The semiconductor structure also includes a seal layer over the air spacer and the gate structure, on a sidewall of the contact etch stop layer, and on a top surface of the nanostructures. A portion of the seal layer is below the air spacer.

Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.