Abstract: A package structure includes a package substrate, an interposer module, a package lid, and a heat dissipation structure between the interposer module and the package lid, including a thermal interface material (TIM) layer, and a metal barrier layer between the TIM layer and at least one of the interposer module or the package lid, and configured to inhibit formation of an intermetallic compound (IMC) layer. A method of making the package structure includes forming a metal barrier layer comprising Cu (111) on at least one of an interposer module or a package lid, attaching the interposer module, forming a thermal interface material (TIM) layer over the interposer module, and attaching the package lid to the package substrate so that the interposer module, the TIM layer and the metal barrier layer are disposed between the package lid and the package substrate, and the metal barrier layer contacts the TIM layer.

Abstract: A package structure includes a package substrate, a chip on the package substrate, a package lid on the chip, and a structure between the chip and the package lid. The structure may include a thermal interface material (TIM) layer, and a metal layer between the TIM layer and at least one of the chip or the package lid and configured to inhibit formation of an intermetallic compound (IMC) layer. A method of making the package structure includes forming a metal layer including a high-texture structure on at least one of a chip or a package lid, attaching the chip to a package substrate, forming a thermal interface material (TIM) layer over the chip, and attaching the package lid to the package substrate over the chip so that the chip, the TIM layer and the metal layer are disposed between the package lid and the package substrate.

Abstract: A passive device of a semiconductor substrate and method of making same. The passive device includes first and second top metal components on a substrate core having an insulator substrate. A passivation layer is formed over the top metal components and insulator substrate. A first conductive component is formed on the passivation layer electrically contacting the first top metal component, as well as a second conductive component that is formed on the passivation layer and electrically contacts the second top metal component. In addition, the device includes an insulator material that is formed over the first conductive component and the second conductive component. A cavity is defined by the insulator material between the first conductive component and the second conductive component. The device further includes an ABF plug component that is formed in the cavity between the first conductive component and the second conductive component.

Abstract: One aspect of the present disclosure pertains to an IC packaging structure that includes a bottom circuit structure having first semiconductor devices on a first substrate, a first interconnect structure over the first semiconductor devices, and a first bonding structure over the first interconnect structure; and a top circuit structure having second semiconductor devices on a second substrate, a second interconnect structure underlying the second semiconductor devices, and a second bonding structure underlying the second interconnect structure. The first bonding structure includes a first metal feature having a first crystalline bulk layer of a metal and a first amorphous surface layer of the metal. The second bonding structure includes a second metal feature having a second crystalline bulk layer of the metal and a second amorphous surface layer of the metal. The top circuit structure is bonded to the bottom circuit structure through the first and second amorphous surface layers.

Abstract: A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.

Abstract: A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy pattern disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy pattern and the contact pad.

Abstract: A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy and the contact pad.