Abstract: A chip stacking and packaging structure includes a substrate, a first chip stacked on the substrate, a heat dissipation module, and a second chip stacked on the heat dissipation module. First bonding pads and second bonding pads are arranged on the substrate. First welding pins are arranged on the first chip. The first welding pins one-to-one cover and are one-to-one electrically connected to the first bonding pads. The heat dissipation module includes a first groove, a cooling liquid cavity, a liquid inlet, a liquid outlet, and first conductive columns. The first chip is embedded in the first groove. A side wall and a bottom wall of the first groove extend into the cooling liquid cavity. Each of the first conductive columns is electrically connected with a corresponding second bonding pad. Each of second welding pins of the second chip is electrically connected to a corresponding first conductive column.

Abstract: A chip stacking and packaging structure includes a substrate, a first chip stacked on the substrate, a heat dissipation module, and a second chip stacked on the heat dissipation module. First bonding pads and second bonding pads are arranged on the substrate. First welding pins are arranged on the first chip. The first welding pins one-to-one cover and are one-to-one electrically connected to the first bonding pads. The heat dissipation module includes a first groove, a cooling liquid cavity, a liquid inlet, a liquid outlet, and first conductive columns. The first chip is embedded in the first groove. A side wall and a bottom wall of the first groove extend into the cooling liquid cavity. Each of the first conductive columns is electrically connected with a corresponding second bonding pad. Each of second welding pins of the second chip is electrically connected to a corresponding first conductive column.

Abstract: The present disclosure provides a chip packaging device, a chip packaging method, and a package chip, and is related to a technical field of chip packaging. The chip packaging device includes conductive sheets, a vacuum suction movable assembly defining a variable suction surface, and a heating assembly. The variable suction surface sucks the plurality of conductive sheets. A first end of each of the conductive sheets is disposed above a corresponding bonding pads. A second end of each of the conductive sheets is disposed above a corresponding welding pin, so that when the variable suction surface is pressed down, the first end of each of the conductive sheets is pressed onto the corresponding bonding pad, and the second end of each of the conductive sheets is pressed onto the corresponding welding pin. The heating assembly heats solders on the bonding pads and the welding pins.

Abstract: A storage device and a storage control method where the storage device includes a flash memory controller, an artificial intelligence (AI) processor and a flash memory storage chip set. The flash memory controller is connected with the AI processor and the flash memory storage chip set separately. The flash memory controller is configured to send original data to be stored to the AI processor when receiving an AI extension instruction from a host, and store tag data from the AI processor in the flash memory storage chip set. The AI processor is configured to convert the original data from the flash memory controller into the tag data by a predetermined algorithm and send the tag data to the flash memory controller. The flash memory controller stores the tag data in the flash memory storage chip set.

Abstract: A storage device and a storage control method where the storage device includes a flash memory controller, an artificial intelligence (AI) processor and a flash memory storage chip set. The flash memory controller is connected with the AI processor and the flash memory storage chip set separately. The flash memory controller is configured to send original data to be stored to the AI processor when receiving an AI extension instruction from a host, and store tag data from the AI processor in the flash memory storage chip set. The AI processor is configured to convert the original data from the flash memory controller into the tag data by a predetermined algorithm and send the tag data to the flash memory controller. The flash memory controller stores the tag data in the flash memory storage chip set.

Abstract: The present invention relates to a detection method used in a memory card adaptor and, more particularly, to a detection method used in an adaptor capable of inserting various kinds of memory cards. The present invention comprises mainly the steps of: a control device on an adaptor issuing an identification command to detect a memory card responsive to the identification command, and the control device issuing again a reset command to detect a reset-type memory card if there is no corresponding response; the control device continually awaiting a response signal if there is still no corresponding response; the control device entering a read/write mode corresponding to the memory card if a corresponding response is obtained after issuing the command; and the control device awaiting a read/write command of said master device. The present invention can effectively enhance detection and identification efficiency without the need of adding a hardware switching device.

Abstract: A memory array apparatus with shorter data accessing time is proposed. The memory array apparatus comprises a register administrator and a plurality of data registers between a micro controller and at least one memory array. The data to be accessed are divided into a plurality of data blocks according to a predetermined data unit. The data block is firstly stored in corresponding data register and then read by the main frame or stored into the corresponding memory array. At the same time, the next data block is stored in the corresponding data register through circuit switched by the micro controller. The pending time of the main frame and the data accessing time can be advantageously reduced.

Abstract: The present invention relates to an algorithm of flash memory capable of quickly building a mapping table and preventing disorder of data due to abnormal disconnection and a control system thereof, wherein pages of a physical block store data of the mapping table of logical block addresses and corresponding physical block addresses. A set of ECC data are used for protection. When the host computer is normally turned on, data of the mapping table are directly stored into a buffer so that the control device can read. The system can quickly build the mapping table to save the time and operation of turning on without the need of a scanning procedure. If an error of the mapping table due to improper operation occurs, the previous mapping table can be retraced to restore the system to the normal state.

Abstract: The present invention proposes a control device compatible to Smart Media cards, Memory Stick cards, and NAND-gate type flash memories and applicable to various kinds of capacities and a method for fabricating same. After the control device is turned on and scans physical block addresses of each data block of a memory card one by one, it will partition the memory card into a plurality of segments according to the capacity of a segment lookup table therein. A FAT accessory lookup table in the control device is matched and used for lookup of logical addresses of the FAT. When a host computer is to access a file, the segment lookup table can be used for lookup of data in the segment, and the FAT accessory lookup table will match the operation system to quick find the physical block address when the FAT is accessed. The control device can be compatible to flash memory cards of various kinds of capacities, and the required size of the size of total lookup tables built in RAM can be effectively controlled.

Abstract: The present invention relates to a detection method used in a memory card adaptor and, more particularly, to a detection method used in an adaptor capable of inserting various kinds of memory cards. The present invention comprises mainly the steps of: a control device on an adaptor issuing an identification command to detect a memory card responsive to the identification command, and the control device issuing again a reset command to detect a reset-type memory card if there is no corresponding response; the control device continually awaiting a response signal if there is still no corresponding response; the control device entering a read/write mode corresponding to the memory card if a corresponding response is obtained after issuing the command; and the control device awaiting a read/write command of said master device. The present invention can effectively enhance detection and identification efficiency without the need of adding a hardware switching device.

Abstract: The present invention proposes a control device compatible to Smart Media cards, Memory Stick cards, and NAND-gate type flash memories and applicable to various kinds of capacities and a method for fabricating same. After the control device is turned on and scans physical block addresses of each data block of a memory card one by one, it will partition the memory card into a plurality of segments according to the capacity of a segment lookup table therein. A FAT accessory lookup table in the control device is matched and used for lookup of logical addresses of the FAT. When a host computer is to access a file, the segment lookup table can be used for lookup of data in the segment, and the FAT accessory lookup table will match the operation system to quick find the physical block address when the FAT is accessed. The control device can be compatible to flash memory cards of various kinds of capacities, and the required size of the size of total lookup tables built in RAM can be effectively controlled.

Abstract: The present invention relates to an algorithm of flash memory capable of quickly building a mapping table and preventing disorder of data due to abnormal disconnection and a control system thereof, wherein pages of a physical block store data of the mapping table of logical block addresses and corresponding physical block addresses. A set of ECC data are used for protection. When the host computer is normally turned on, data of the mapping table are directly stored into a buffer so that the control device can read. The system can quickly build the mapping table to save the time and operation of turning on without the need of a scanning procedure. If an error of the mapping table due to improper operation occurs, the previous mapping table can be retraced to restore the system to the normal state.

Abstract: The present invention relates to a flash memory and, more particularly, to an and-gate type flash memory, wherein a plurality of data storage units are provided, each of the data storage units is partitioned into a plurality of sectors, and an ECC data directly abuts behind each of the sectors to store the ECC of the sector, thereby shortening the access time of data when the data storage unit is not filled. At least a dynamic spare storage unit not detectable by a mainframe is provided in the data storage unit. When a sector of a flash memory is damaged, a control device is used to store the data in the damaged storage unit into the dynamic spare storage unit, thereby decreasing the number of damaged storage units detectable by the mainframe to relatively lengthen the lifetime of use of the flash memory.

Abstract: A memory array apparatus with shorter data accessing time is proposed. The memory array apparatus comprises a register administrator and a plurality of data registers between a micro controller and at least one memory array. The data to be accessed are divided into a plurality of data blocks according to a predetermined data unit. The data block is firstly stored in corresponding data register and then read by the main frame or stored into the corresponding memory array. At the same time, the next data block is stored in the corresponding data register through circuit switched by the micro controller. The pending time of the main frame and the data accessing time can be advantageously reduced.