Patents by Inventor Chen PAN

Chen PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12293922
    Abstract: The present application provides a reworking method of a failed hard mask layer on a via opening in a dielectric layer, including removing the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 6, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wei-Chen Pan
  • Publication number: 20250069947
    Abstract: The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer includes tantalum, and the assisting blocking layer includes copper manganese alloy.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Inventor: WEI-CHEN PAN
  • Patent number: 12230535
    Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack; and forming a via in the via opening and a trench in the trench opening. The translucent layer includes a mask opening of via feature which exposes a portion of the mask substrate. A thickness of the trench region is less than a thickness of the mask region.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 18, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wei-Chen Pan
  • Publication number: 20250029871
    Abstract: A method for fabricating a semiconductor device includes: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.
    Type: Application
    Filed: October 8, 2024
    Publication date: January 23, 2025
    Inventor: WEI-CHEN PAN
  • Publication number: 20250014910
    Abstract: The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.
    Type: Application
    Filed: September 16, 2024
    Publication date: January 9, 2025
    Inventor: WEI-CHEN PAN
  • Patent number: 12191194
    Abstract: The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: January 7, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wei-Chen Pan
  • Patent number: 12159790
    Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes: providing a photomask comprising an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; providing a device stack comprising a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer; forming a pre-process mask layer on the device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer comprising a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature. The method also includes performing a damascene etching process to form a via opening in the first dielectric layer and a trench opening in the second dielectric layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: December 3, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wei-Chen Pan
  • Patent number: 12142518
    Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: November 12, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wei-Chen Pan
  • Publication number: 20240304116
    Abstract: A storage box includes an electronic device, a box body, and an electronic label module, wherein an edition application program of the electronic device sends product information. The electronic label module is disposed on the box body and includes an induction antenna receiving an information stream containing the product information and a current; a rectifier circuit collecting and stabilizing the current; a microprocessor receiving the information stream and converting a format of the product information; and an electronic ink screen receiving the current provided by the rectifier circuit, triggered by the current, and receiving the information stream from the microprocessor, and presenting the product information. The storage box of the present invention can update the picture on the screen and present the product information on the screen without using a power supply.
    Type: Application
    Filed: February 20, 2024
    Publication date: September 12, 2024
    Inventors: JUN-SHENG LIN, YI-CHEN PAN
  • Publication number: 20240303900
    Abstract: A method, an apparatus and a system for graphics rendering based on a Web Graphics Library (WebGL) are provided. The method includes that: initial rendering information is acquired; the initial rendering information is converted according to a preset layer encapsulation format to obtain layer rendering data; the layer rendering data is mapped into a WebGL data format to obtain WebGL rendering data; and a WebGL interface is invoked and rendering output is performed according to the WebGL rendering data. According to the method, an element drawn by the WebGL is encapsulated into a layer, the layer rendering data is acquired in a form of preset layer encapsulation format, and then the layer rendering data is mapped into the WebGL data format, so that the underlying drawing ability is opened to a web application layer.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 12, 2024
    Applicant: GAODING (XIAMEN) TECHNOLOGY CO., LTD
    Inventors: Chen PAN, Ze ZHENG
  • Publication number: 20240237326
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: October 25, 2022
    Publication date: July 11, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240237327
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: July 18, 2023
    Publication date: July 11, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240138138
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20240138139
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 25, 2024
    Inventors: SHIH-FAN KUAN, WEI-CHEN PAN, YU-TING LIN, HUEI-RU LIN
  • Publication number: 20230317512
    Abstract: The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventor: WEI-CHEN PAN
  • Publication number: 20230317514
    Abstract: The present application discloses a semiconductor device with a composite barrier structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first dielectric layer having a feature opening on a substrate; a composite barrier structure in the feature opening, wherein the composite barrier structure includes a barrier layer in the feature opening and an assisting blocking layer on the barrier layer; and a conductive feature on the assisting blocking layer; wherein the barrier layer comprises tantalum, and the assisting blocking layer comprises copper manganese alloy.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventor: WEI-CHEN PAN
  • Publication number: 20230317508
    Abstract: The present application discloses a method for fabricating the semiconductor device. The method for fabricating the semiconductor device includes forming a first dielectric layer on a substrate; forming a feature opening to exposing the substrate; performing a pre-cleaning treatment including a pre-cleaning solution to the feature opening; performing a cleaning process to the feature opening; and forming a conductive feature in the feature opening. The pre-cleaning solution includes a chelating agent and a corrosion inhibitor.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: WEI-CHEN PAN, CHUN-WEI WANG
  • Publication number: 20230317468
    Abstract: The present application provides a reworking method of a failed hard mask layer on a via opening in a dielectric layer, including removing the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventor: WEI-CHEN PAN
  • Publication number: 20230307289
    Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventor: WEI-CHEN PAN
  • Publication number: 20230307248
    Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes: providing a photomask comprising an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; providing a device stack comprising a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer; forming a pre-process mask layer on the device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer comprising a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature. The method also includes performing a damascene etching process to form a via opening in the first dielectric layer and a trench opening in the second dielectric layer.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventor: WEI-CHEN PAN