Abstract: A plasma processing apparatus adapted to reduce non-uniformity of plasma distribution in a process chamber and to adjust the plasma distribution to “centrally high density”, “circumferentially high density”, or “uniform density” in accordance with a desired etching process, a process chamber; a radio frequency power source; a rectangular waveguide; and a circular waveguide connected to the rectangular waveguide, in which the rectangular waveguide includes an upper rectangular waveguide and a lower rectangular waveguide formed by vertically dividing the rectangular waveguide; and a cutoff section which cuts off the microwave frequency power and which has a dielectric body. The circular waveguide includes an inner waveguide connected to the upper rectangular waveguide and formed inside; and an outer waveguide connected to the lower rectangular waveguide and formed on an outer side of the inner waveguide. The cutoff section has a width narrower than those of the rectangular waveguides except the cutoff section.

Abstract: A plasma processing apparatus adapted to reduce non-uniformity of plasma distribution in a process chamber and to adjust the plasma distribution to “centrally high density”, “circumferentially high density”, or “uniform density” in accordance with a desired etching process, a process chamber; a radio frequency power source; a rectangular waveguide; and a circular waveguide connected to the rectangular waveguide, in which the rectangular waveguide includes an upper rectangular waveguide and a lower rectangular waveguide formed by vertically dividing the rectangular waveguide; and a cutoff section which cuts off the microwave frequency power and which has a dielectric body. The circular waveguide includes an inner waveguide connected to the upper rectangular waveguide and formed inside; and an outer waveguide connected to the lower rectangular waveguide and formed on an outer side of the inner waveguide. The cutoff section has a width narrower than those of the rectangular waveguides except the cutoff section.

Abstract: A plasma processing apparatus includes: a vacuum chamber that includes a plasma processing chamber in which a substrate is to be plasma-processed and that can exhaust an inside of the plasma processing chamber to vacuum; and a microwave power supply unit that supplies a microwave power to the vacuum chamber via a circular waveguide. The vacuum chamber includes: a parallel flat plate line portion that is connected to the circular waveguide and receives a microwave power propagated from the circular waveguide; a ring resonator unit that is disposed on an outer periphery of the parallel flat plate line portion and receives the microwave power propagated from the parallel flat plate line portion; a cavity portion that receives a microwave power radiated from a slot antenna formed in the ring resonator unit; and a microwave introduction window that separates the cavity portion from the plasma processing chamber.

Abstract: In order to enable plasma density distribution control having a high degree of freedom to solve problems of not only in-plane uniformity of an etching processing but also a reduction of a charge-up damage, a plasma processing apparatus includes: a vacuum chamber provided with a plasma processing chamber that plasma-processes a substrate inside and is able to exhaust the inside of this plasma processing chamber to a vacuum; and a microwave power supply unit that is provided with a microwave source and a circular waveguide and supplies, via the circular waveguide, a microwave power oscillated from the microwave source to the vacuum chamber, in which the microwave power supply unit is configured by arranging a plurality of waveguides, which are coaxially and concentrically arranged with the circular waveguide and have different dielectric constants inside, between the circular waveguide and the vacuum chamber.

Abstract: Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.

Abstract: Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.

Abstract: Provided is a manufacturing method of a sensor including the following steps. A mold having a cavity is provided. At least one chip is disposed in the cavity. The chip has an active surface and a back surface opposite to each other. The active surface faces toward a bottom surface of the cavity. A polymer material is filled in the cavity to cover the back surface of the chip. A heat treatment is performed, such that the polymer material is solidified to form a polymer substrate. A mold release treatment is performed to isolate the polymer substrate from the cavity. A plurality of conductive lines are formed on a first surface of the polymer substrate. The conductive lines are electrically connected with the chip.

Abstract: A method for analyzing concentration of a cardiovascular disease (CVD) biomarker in a liquid sample includes: applying the liquid sample to a biosensor, the biosensor including a transistor having a drain, a source, and a gate terminal disposed between the gate and the source, and a reactive electrode spaced apart from the gate terminal of the transistor and having a receptor immobilized thereon for specific binding with the CVD biomarker, the liquid sample being in contact with the gate terminal and the reactive electrode; applying a voltage pulse between the reactive electrode and the source, the voltage pulse having a pulse width; monitoring a response current in response to the voltage pulse; and analyzing the response current.

Abstract: A method for analyzing concentration of an analyte in a liquid sample applied to a biosensor includes: applying a voltage pulse to the liquid sample applied to the biosensor, the voltage pulse having a pulse width of not greater than 10?3 second; monitoring a response current, which is produced in response to the voltage pulse, within the pulse width via electrodes of the biosensor; and analyzing the response current that is correlated to the concentration of the analyte in the liquid sample.

Abstract: Provided is a manufacturing method of a sensor including the following steps. A mold having a cavity is provided. At least one chip is disposed in the cavity. The chip has an active surface and a back surface opposite to each other. The active surface faces toward a bottom surface of the cavity. A polymer material is filled in the cavity to cover the back surface of the chip. A heat treatment is performed, such that the polymer material is solidified to form a polymer substrate. A mold release treatment is performed to isolate the polymer substrate from the cavity. A plurality of conductive lines are formed on a first surface of the polymer substrate. The conductive lines are electrically connected with the chip.

Abstract: A method for analyzing concentration of a cardiovascular disease (CVD) biomarker in a liquid sample includes: applying the liquid sample to a biosensor, the biosensor including a transistor having a drain, a source, and a gate terminal disposed between the gate and the source, and a reactive electrode spaced apart from the gate terminal of the transistor and having a receptor immobilized thereon for specific binding with the CVD biomarker, the liquid sample being in contact with the gate terminal and the reactive electrode; applying a voltage pulse between the reactive electrode and the source, the voltage pulse having a pulse width; monitoring a response current in response to the voltage pulse; and analyzing the response current.

Abstract: A method for analyzing concentration of an analyte in a liquid sample applied to a biosensor includes: applying a voltage pulse to the liquid sample applied to the biosensor, the voltage pulse having a pulse width of not greater than 10?3 second; monitoring a response current, which is produced in response to the voltage pulse, within the pulse width via electrodes of the biosensor; and analyzing the response current that is correlated to the concentration of the analyte in the liquid sample.

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

Abstract: A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure.

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

Abstract: A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.