Patents by Inventor Chen-Ping Hsu

Chen-Ping Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12169308
    Abstract: A method of using a coupling system includes aligning an optical fiber with a cavity in a chip, wherein aligning the optical fiber comprises orienting the fiber within an angle ranging from about 88-degrees to about 92-degrees with respect to a top surface of the chip. The method further includes emitting an optical signal from the optical fiber. The method further includes redirecting the optical signal into a waveguide using a grating positioned on an opposite side of the cavity from the optical fiber.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
  • Patent number: 12153255
    Abstract: A method of making a photonic device includes depositing a cladding layer over a silicon layer. The method further includes patterning the cladding layer to expose a first portion of the silicon layer, wherein a second portion of the silicon layer is covered by the patterned cladding layer, and a waveguide portion is in the second portion of the silicon layer. The method further includes depositing a low refractive index layer directly over the patterned cladding layer, wherein a refractive index of the low refractive index layer is less than a refractive index of silicon nitride.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Ying Wu, Yuehying Lee, Sui-Ying Hsu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
  • Patent number: 12156478
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: November 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 12146927
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
    Type: Grant
    Filed: October 4, 2023
    Date of Patent: November 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20240379820
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Publication number: 20240361532
    Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a grating on a first side of a semiconductor layer, wherein the grating is configured to receive the optical signal. The coupling system further includes an interconnect structure over the grating on the first side of the semiconductor layer, wherein the interconnect structure defines a cavity aligned with the grating. The coupling system further includes a first polysilicon layer on a second side of the semiconductor layer, wherein the second side of the semiconductor layer is opposite to the first side of the semiconductor layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Chen-Hao HUANG, Hau-Yan LU, Sui-Ying HSU, Yuehying LEE, Chien-Ying WU, Chien-Chang LEE, Chia-Ping LAI
  • Patent number: 12108871
    Abstract: A brush roller and its manufacturing method and brush roller mold is provided, the brush roller is manufactured by foaming a gaseous pore filler, while solving the problem of using a solid pore filler foaming method to manufacture the brush roller. In addition, the brush roller of the present invention has a plurality of fluid channels communicating between any adjacent two, and the plurality of fluid channels respectively extend to the surface of the brush roller to form pores to improve the fluid permeability of the brush roller, and in the brush roller manufacturing method of the present invention, after the PVA emulsified solution is cured, the compressive stress under the condition of the predetermined compression ratio can be formed to meet the expected brush roller, and it can be used to brush the circuit substrate.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: October 8, 2024
    Assignee: Cenefom Corp.
    Inventor: Chen-Ping Hsu
  • Patent number: 12107149
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Patent number: 12072534
    Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a chip in optical communication with the optical fiber. An angle between the optical fiber and a top surface of the chip ranges from about 92-degrees to about 88-degrees. The chip includes a grating configured to receive the optical signal; and a waveguide, wherein the grating is configured to receive the optical signal and redirect the optical signal along the waveguide. ms.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chen-Hao Huang, Chien-Chang Lee, Chia-Ping Lai
  • Patent number: 12050348
    Abstract: A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chien-Chang Lee, Chia-Ping Lai
  • Publication number: 20220125193
    Abstract: A brush roller and its manufacturing method and brush roller mold is provided, the brush roller is manufactured by foaming a gaseous pore filler, while solving the problem of using a solid pore filler foaming method to manufacture the brush roller. In addition, the brush roller of the present invention has a plurality of fluid channels communicating between any adjacent two, and the plurality of fluid channels respectively extend to the surface of the brush roller to form pores to improve the fluid permeability of the brush roller, and in the brush roller manufacturing method of the present invention, after the PVA emulsified solution is cured, the compressive stress under the condition of the predetermined compression ratio can be formed to meet the expected brush roller, and it can be used to brush the circuit substrate.
    Type: Application
    Filed: October 19, 2021
    Publication date: April 28, 2022
    Inventor: CHEN-PING HSU
  • Patent number: 10143477
    Abstract: A hemostatic equipment has a pallet and an inflatable pillar. The pallet has a holder used for a patient to hold, providing foolproof effect in an operation direction to ensure that the inflatable pillar may enter a nasal cavity of a patient in a correct direction. The inflatable pillar has a head exposed with a pressing surface for pressing a bleeding site inside a nasal cavity of a patient to stop bleeding.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: December 4, 2018
    Assignee: CENEFOM CORP.
    Inventor: Chen-Ping Hsu
  • Publication number: 20160235953
    Abstract: A hemostatic equipment has a pallet and an inflatable pillar. The pallet has a holder used for a patient to hold, providing foolproof effect in an operation direction to ensure that the inflatable pillar may enter a nasal cavity of a patient in a correct direction. The inflatable pillar has a head exposed with a pressing surface for pressing a bleeding site inside a nasal cavity of a patient to stop bleeding.
    Type: Application
    Filed: September 1, 2015
    Publication date: August 18, 2016
    Inventor: CHEN-PING HSU
  • Publication number: 20140309609
    Abstract: A medical dressing for trauma injuries is disclosed. The dressing includes a base, a porous foam layer and a protective film. The base has a muffling side. The porous foam layer is partially attached on the muffling side. The protective film covers the muffling side and the porous foam layer.
    Type: Application
    Filed: June 3, 2013
    Publication date: October 16, 2014
    Applicant: CENEFOM CORP.
    Inventor: Chen-Ping Hsu