Abstract: An image pickup device includes a main body, in which a processing unit is provided to electrically connect to a front image pickup unit mounted on a front side of the main body, an image display unit mounted to one side of the main body, a rear image pickup unit mounted on a rear side of the main body, and a memory unit and a power supply unit mounted in the main body. The processing unit has an image combination processing module for combining images picked up by the front and the rear image pickup unit into one image. With this design, images in front of and behind the image pickup device can be simultaneously captured and then combined into one to provide a photographer with more flexibility and fun in using the image pickup device.

Abstract: An imaging apparatus includes an audio/video capture mechanism and an output mechanism movably installed at a side of the audio/video capture mechanism, and the output mechanism includes a first display unit and a second display unit installed on both surfaces of the output mechanism respectively and coupled to the audio/video capture mechanism, such that the imaging apparatus can display a captured image by the first and second display units and allow a photographer to view the content of a captured image while taking the picture of his own, as well as allowing the photographer and a photographed party to simultaneously view the content of a capture image, so as to achieve a more practical photographical effect to cope with different requirements.

Abstract: An imaging apparatus includes an audio/video capture mechanism having an audio/video processing unit, an image synchronization unit, a first imaging unit, a second imaging unit and a sound input/output unit; and an output mechanism movably installed on a side of the audio/video capture mechanism, and including a display unit installed on a surface of the output mechanism and coupled to the audio/video capture mechanism, and the second imaging unit is installed on another surface of the output mechanism, such that when the imaging apparatus is used for taking a picture, the first and second imaging units are used for capturing images from a same viewing angle, and the image synchronization unit is provided for synchronously combining the images to form a three-dimensional (3D) image, so as to achieve the effects of capturing and playing the 3D image.

Abstract: An image pickup device includes a main body, an image pickup assembly, and a cover. The image pickup assembly is located in the main body and has an image pickup section and an infrared emitter section. The image pickup section has a lens, a light filter, and a light sensing element. The light filter is located between the lens and the light sensing element to allow visible light and infrared light of a predetermined wavelength to pass therethrough and reach at the light sensing element. The cover is located on the main body to cover the image pickup assembly, and has an image pickup window positioned corresponding to the image pickup section and an emission window positioned corresponding to the infrared emitter section. With these arrangements, the image pickup device can be used to pick up images of an object in a fully dark environment.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.

Abstract: A multimedia playing device includes a central processing unit, a plurality of sensors electrically coupled to the central processing unit, and an output unit electrically coupled to the central processing unit. The plurality of sensors are operated together with the central processing unit, such that after the sensors detect different hand movements of a user, the central processing unit reads and determines the hand movement and transmits related control signals to the output unit according to different hand movements to achieve the effects of using a hand posture to control related functional movements and enhancing the convenience of using the multimedia playing device.

Abstract: In one embodiment, a node comprises a plurality of interface circuits coupled to a node controller. Each of the plurality of interface circuits is configured to couple to a respective link of a plurality of links. The node controller is configured to select a first link from two or more of the plurality of links to transmit a first packet, wherein the first link is selected responsive to a relative amount of traffic transmitted via each of the two or more of the plurality of links.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.

Abstract: The present invention provides a device for handling requests for changing system mode. The device includes a signal hold/clear unit and a gate control unit. The signal hold/clear unit has the first input receiving a request signal, the second input receiving a control signal, and an output holding the request signal. Wherein, the signal hold/clear unit clears the request signal being held while the control signal is active. The gate control unit has the first input connected to the first input of the signal hold/clear unit, the second input connected to the output of the signal hold/clear unit, the third input connected to the second input of the signal hold/clear unit, and an output. Wherein, the gate control unit passes the request signal while the control signal is active, otherwise blocks the request signal.

Abstract: A peripheral device interface control chip having a cache system therein and a method of synchronization data transmission between the cache system and an external device in a computer system. The cache system and data synchronization method can be applied to the peripheral device interface control chip having a data buffer and a peripheral device interface controller. The data buffer is located inside the control chip for holding data stream read from a memory unit so that data required by the peripheral device is provided. When the data stream is still valid, the data stream is retained. The peripheral device interface controller is installed inside the control chip. The peripheral device interface controller detects if the data stream inside the data buffer includes the data required by the peripheral device and whether the data stream is still valid or not.

Abstract: The present invention provides a device for handling requests for changing system mode. The device includes a signal hold/clear unit and a gate control unit. The signal hold/clear unit has the first input receiving a request signal, the second input receiving a control signal, and an output holding the request signal. Wherein, the signal hold/clear unit clears the request signal being held while the control signal is active. The gate control unit has the first input connected to the first input of the signal hold/clear unit, the second input connected to the output of the signal hold/clear unit, the third input connected to the second input of the signal hold/clear unit, and an output. Wherein, the gate control unit passes the request signal while the control signal is active, otherwise blocks the request signal.

Abstract: A PCI data accessing system with a read request pipeline and an application method thereof are provided. The PCI data accessing system has a PCI master device, a memory module, and a PCI control device. The PCI master device issues a first read request, and the PCI control device converts the first read request to a second read request divided into a first part and a second part. Each part of the second request requests one line data, i.e. 64 bits data. The memory module stores data requested by the PCI master device. Moreover, there is no latency time between data for the first part and the second part returned from the memory module.

Abstract: A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with respect to the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator, indicating that the request has been accepted. When the requested data is ready in the responder, the responder will forward the defer identifier again.

Abstract: A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit. The cache system has a two-way first-in first-out buffer region and a two-way cache controller. The two-way first-in first-out buffer region further has a first cache data region and a second cache data region. The first cache data region and the second cache data region are capable of holding a batch of first cache data and a batch of second cache data. The two-way cache controller receives a read request from the peripheral device. According to the read request, the requested data and data that ensues or comes after the requested data are retained by the two-way first-in first-out buffer (FIFO) region.

Abstract: A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

Abstract: A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

Abstract: Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.

Abstract: A two-way cache system and operating method for interfacing with peripheral devices. The cache system is suitable for data transmission between a peripheral device and a memory unit and has a two-way first-in first-out buffer region and a two-way cache controller. The two-way first-in first-out buffer region further has a first cache data region and a second cache data region. The first cache data region and the second cache data region are capable of holding a batch of first cache data and a batch of second cache data. The two-way cache controller receives a read request signal from the peripheral device. According to the read request, the requested data and the data that comes after the requested data are retained by the two-way first-in first-out buffer region. If the peripheral device continues to request more data, the first cache data region and the second cache data region are alternately used to read in subsequent data.