Abstract: A solar cell includes a silicon substrate, a passivation layer, a first protection layer, a second protection layer, and a third protection layer. The material of the passivation layer is aluminum oxide, and the passivation layer is on the lower surface of the silicon substrate. The material of the first protection layer is silicon oxynitride, and the first protection layer is on a surface of the passivation layer opposite to the silicon substrate. The material of the second protection layer is silicon nitride, and the second protection layer is on a surface of the first protection layer opposite to the passivation layer. The material of the third protection layer is silicon oxynitride or silicon oxide, and the third protection layer is on a surface of the second protection layer opposite to the first protection layer.

Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.