Patents by Inventor Chen-Rui Tseng

Chen-Rui Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9744624
    Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 ?m for fine line width/pitch.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 29, 2017
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Jaen-Don Lan, Pin-Chung Lin, Chen-Rui Tseng, Cheng-En Ho, Yu-An Chen
  • Publication number: 20160374206
    Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 ?m for fine line width/pitch.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Jaen-Don Lan, PIN-CHUNG LIN, CHEN-RUI TSENG, CHENG-EN HO, YU-AN CHEN
  • Publication number: 20160372409
    Abstract: Disclosed is a circuit board structure, including the first, second and third metal layers sequentially stacked on the substrate from bottom to top and formed by the sputtering process, the chemical plating process and the electroplating process, respectively. The substrate includes the stop layer and the resin layer stacked on the stop layer. The stop layer includes a pattern having at least one contact region, which is not covered by the resin layer. The first, second and third metal layers have an etched circuit pattern, respectively, and each of the etched circuit patterns is provided out of the corresponding contact region and aligned to each other to expose part of the resin layer. The etched circuit pattern is used for electrical connection. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and more stable.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Jaen-Don Lan, PIN-CHUNG LIN, CHEN-RUI TSENG, CHENG-EN HO, YU-AN CHEN
  • Patent number: 8502544
    Abstract: A method for testing a mask article includes the steps of electrically connecting the mask article to an electrical sensor, applying a bias voltage to a plurality of testing sites of the mask article with a conductor, measuring at least one current distribution of the testing sites with the electrical sensor, and determining the quality of the mask article by taking the at least one current distribution into consideration.
    Type: Grant
    Filed: July 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Taiwan Mask Corporation
    Inventors: Ming-Chih Chen, Hsiang-Jen Yang, Chen-Rui Tseng