Patents by Inventor Chen-Shao Hsu

Chen-Shao Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210125847
    Abstract: A method of making a transfer head for transferring micro elements, wherein the transfer head includes a cavity with a plurality of vacuum paths and a suite having arrayed suction nozzles and vacuum paths. The suction nozzles are connected to the vacuum path components respectively, and the vacuum path components are formed to connect to vacuum paths in the cavity respectively. The suction nozzles attract or release the micro element through vacuum pressure transmitted by vacuum. When the suite is mounted in the cavity, the upper surface of the suite is arranged with optical switching components for controlling the switch of the vacuum path components and vacuum paths of each path so that the suction nozzles can attract or release required micro element through vacuum pressure; and fabricating a suite with an array micro-hole structure, wherein the array micro-hole structure serves as the vacuum path components and the suction nozzles.
    Type: Application
    Filed: December 31, 2020
    Publication date: April 29, 2021
    Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chen-ke HSU, Jiansen ZHENG, Xiaojuan SHAO, Kechuang LIN
  • Publication number: 20210055646
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Patent number: 10816892
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-CHeng Ho, Chen-Shao Hsu
  • Publication number: 20190148110
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 16, 2019
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Patent number: 9377701
    Abstract: In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Publication number: 20150227038
    Abstract: In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.
    Type: Application
    Filed: April 27, 2015
    Publication date: August 13, 2015
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Patent number: 9017903
    Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Patent number: 8999611
    Abstract: Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Publication number: 20150024306
    Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Publication number: 20140255825
    Abstract: Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu