Abstract: The present disclosure provides a network energy saving method and apparatus, a device and a storage medium, which are applied to a network device. First, energy consumption indication information is acquired, which is used for indicating a target energy consumption state of the network device, and then data is transceived based on the target energy consumption state. In the embodiment of the present disclosure, an energy saving approach is configured for the network device, and then the target energy consumption state of the network device is indicated by indication information, so that the network device can determine the corresponding energy saving approach according to the target energy consumption state, thereby reducing the energy consumption of the network device.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: Guided filtering is applied, with a camera raw image as a guidance image, to a first image to generate an intermediate image. A dynamic range mapping is performed on the intermediate image to generate a second image of a different dynamic range. The second image is used to generate specific local reshaping function index values for selecting specific local reshaping functions. The specific local reshaping functions are applied to the second image to generate a locally reshaped image.

Abstract: A method, computer system, and a computer program product for smart SDN is provided. The present invention may include recording and clustering a pod's behavior to generate a behavior transition model for the pod. The present invention may include watching a behavior of the pod and comparing the behavior to the generated behavior transition model. The present invention may include triggering a network policy change based on determining that the behavior of the pod is a misbehavior.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

Abstract: A computer-implemented method for adaptively discretizing a position of a textual object in a document includes receiving, by a computer system, an image of the document and determining, by the computer system, an absolute position of the textual object in the image of the document. The method further includes normalizing, by the computer system, the absolute position to determine a relative position of the textual object. The method also includes calculating, by the computer system, a bin size such that at least one axis of the image is divided into a plurality of separate bins, wherein a distance between each bin along the at least one axis and its adjacent bin equals the bin size. The method includes discretizing, by the computer system, the relative position based on the bin size to determine a discretized position of the textual object; and providing, by the computer system, the discretized position and a textual content of the textual object as an input to a machine learning model.

Abstract: A computer vision processing system is provided. The system includes one or more target devices and a processing unit. The target devices are configured to run the executable code of an image processing pipeline. The processing unit is configured to receive a series of application programming interface (API) calls and create a raw graph accordingly, redraw the raw graph into a compilable graph by sequentially processing each node, and compile the compilable graph into the executable code of the image processing pipeline. The series of API calls includes at least one tiling API call to set at least one of the nodes and at least one of the data objects as tileable. Each tileable node corresponds to multiple parallel processing nodes in multiple branches in the compilable graph, and each tileable data object corresponds to multiple tile data objects in the branches in the compilable graph.

Abstract: A display device has a display area and a peripheral area, and includes an array substrate. The array substrate includes M number of pixel unit columns disposed in the display area and a first dummy electrode disposed in the peripheral area, where M is a positive integer greater than or equal to 2. The M number of pixel unit columns include a first pixel unit column to an Mth pixel unit column arranged in sequence. Each of the M number of pixel unit columns includes a plurality of pixel units arranged in sequence. The first dummy electrode is located on one side of the first pixel unit column. During a frame period, the first pixel unit column receives the first pixel signal, and the first dummy electrode receives the first dummy signal. The polarity of the first pixel signal is different from that of the first dummy signal.

Abstract: An image distortion correction method and an apparatus, where the method includes: performing optical distortion correction on a collected source image to obtain a first corrected image, where the first corrected image includes a background region and a portrait in which stretching deformation occurs, and where the portrait in which stretching deformation occurs includes at least a first human body region in which stretching deformation occurs and a second human body region in which stretching deformation occurs; and performing algorithm constraint correction on the first human body region, the second human body region, and the background region to obtain a second corrected image, where constraint terms used for the algorithm constraint correction respectively constrain the first human body region, the second human body region, and the background region.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: Embodiments of the disclosure discloses a method, apparatus, device and storage medium for network security-based page processing, and relates to the technical field of computer. The method comprises displaying, in an event display page corresponding to a target alarm notification, an event timeline corresponding to the target alarm notification and an object link corresponding to the target alarm notification, the event timeline comprises a plurality of event units, an event unit comprises description information of an associated event of the target alarm notification, the description information comprises an association relationship between associated objects of the associated event, the plurality of event units is sorted and displayed based on occurrence time of associated events; the object link comprises a sub-link corresponding to an object unit, the sub-link comprises an object icon of an associated object, and a connection relationship between object icons corresponds to the association relationship.

Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

Abstract: A driver backplane, display panel, splicing screen and electronic apparatus. The driver backplane includes a drive function layer and a plurality of bonding electrode sets disposed on a side of the drive function layer. In one of the plurality of the bonding electrode columns closest to the first side and serving as a first bonding electrode column, the backup bonding electrodes of at least a part of the bonding electrode sets are disposed on a side of the primary bonding electrodes facing away from the first side.

Abstract: A substrate assembly is provided, including a first substrate, an active element layer, a plurality of first electrodes, a circuit substrate, and a plurality of second electrodes. The active element layer is disposed on the first substrate. The plurality of first electrodes are disposed on the first substrate and arranged along a first direction. The circuit substrate is partially overlapping the first substrate in a vertical projection direction. The plurality of second electrodes are disposed on the circuit substrate. A distance between the edge of one of the plurality of second electrodes and the edge of one of the plurality of first electrodes is greater than zero in the first direction, and a width of the one of the plurality of first electrodes is different from a width of the one of the plurality of second electrodes.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A method performed by a user equipment (UE) is provided that includes receiving, via a RRC signaling, SIB for two uplink carriers in one cell, the two uplink carriers including a first uplink carrier corresponding to a downlink carrier in which a downlink synchronization signal is received and a second uplink carrier, transmitting an uplink signal on one of the two uplink carriers configured to the UE.

Abstract: A method includes performing blind detection on a PDCCH in at least one subframe or slot to acquire first downlink control information and second downlink control information; and performing uplink data transmission and downlink data transmission with a base station according to the acquired first downlink control information and second downlink control information, wherein the first downlink control information is one of downlink control information for uplink scheduling grant and downlink control information for downlink scheduling, and the second downlink control information is the other one of the downlink control information for uplink scheduling grant and the downlink control information for downlink scheduling, and wherein a location where a PDCCH carrying the second downlink control information is detected is associated with related information of the first downlink control information, or the first downlink control information and the second downlink control information are carried on the same PDCCH.

Abstract: A terminal device and a method for measuring cross-link interference. The method includes receiving time-frequency resource configuration information from a base station, wherein the time-frequency resource configuration information includes configuration information of measurement time-frequency resources for measuring the cross-link interference. The method also includes determining measurement time-frequency resources for measuring the cross-link interference according to the time-frequency resource configuration information. The method further includes measuring the cross-link interference on the measured time-frequency resources and feeding back the measurement result of the cross-link interference to the base station.