Abstract: A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.

Abstract: A method for forming a double spacer structure comprising the steps of first providing a semiconductor substrate that has a first gate and a second gate already formed thereon, wherein the gate length of the second gate is greater than the gate length of the first gate. Then, a first insulating layer is formed over the substrate and the gates. Next, a photoresist layer is formed over the first insulating layer above the second gate while exposing the first insulating layer above the first gate. Subsequently, a first etching operation is performed to establish a first spacer structure along the sidewalls of the first gate, and then the photoresist layer is removed leaving the first insulating layer over the second gate. Thereafter, a second insulating layer is formed over the substrate, the first gate and the first insulating layer, and then a second etching operation is performed to establish a second spacer structure along the sidewalls of the second gate.

Abstract: A semiconductor fabrication method that enhances the ESD (electrostatic discharge) protection capability of an ESD protective device provided in an integrated circuit such as a mask-programmed ROM, allows the mask-programmed ROM to be downsized while still providing adequate ESD protection capability, and allows the mask-programmed ROM to be fabricated in a smaller size, while nonetheless providing adequate ESD protection capability for the internal circuit. Initially, a mask for the ion implantation process for the ROM is prepared. The mask is patterned additionally with a plurality of strips used to define breakdown voltage controlling areas in the ESD protective device. Then, the ion implantation process is performed through the mask so as to form the breakdown voltage controlling areas each beneath the drain of the n-type CMOS transistor.