Abstract: A method for producing a polyester polyol is provided, which includes: feeding a first antioxidant and a raw material reactant that includes a polyacid and a polyol into a reactor; subjecting the polyacid and the polyol to an esterification reaction to form an oligomer; and performing a prepolymerization reaction on the oligomer to obtain a prepolymerization reactant. During the prepolymerization reaction, the method includes sampling and monitoring an acid value of the prepolymerization reactant. When the acid value of the prepolymerization reactant reaches a first acid value, an esterification reaction catalyst is added to the prepolymerization reactant for carrying out a polycondensation reaction and generating a polycondensation reactant that contains the polyester polyol. During the polycondensation reaction, the method includes sampling and monitoring an acid value of the polycondensation reactant.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method of monitoring a semiconductor process includes the following steps. A process parameter is set to a first condition. A first process is performed to form a first film layer on a first wafer. The first film layer does not cover a wafer edge region of the first wafer. The first wafer having the first film layer is photographed by an image capturing device to obtain a first wafer image. Image recognition is performed to the first wafer image to obtain first data. Whether a position of the first film layer is offset is determined according to the first data.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: A method of monitoring a semiconductor process includes the following steps. A process parameter is set to a first condition. A first process is performed to form a first film layer on a first wafer. The first film layer does not cover a wafer edge region of the first wafer. The first wafer having the first film layer is photographed by an image capturing device to obtain a first wafer image. Image recognition is performed to the first wafer image to obtain first data. Whether a position of the first film layer is offset is determined according to the first data.

Abstract: A geared generator for an electric vehicle has a body, a gearing device, a hub device and an electromotor. The body has two mounting boards, a battery and a commutator connected to the battery. The gearing device is connected to the body and has a primary tube, a minor tube, a gear-up segment, an output shaft, a mounting jacket, a stator mount and a motor stator. The gear-up segment is rotatably mounted between the gear disks and has three transmission shafts, three planet gear wheels and multiple bearings. The hub device is mounted around the tubes between the mounting boards and has two hub disks and a hub ring. The hub ring has a spacing disk and two side rings. The electromotor is connected to the gearing device and has a base, a coil stator, an eccentric flywheel, a fan and a protecting hood.

Abstract: A gearing generator for an electric vehicle has a body, a gearing device, a hub device and an electromotor. The body has two mounting boards, a battery and a commutator connected to the battery. The gearing device is connected to the body and has a primary tube, a minor tube, a gear-up segment, an output shaft, a mounting jacket, a stator mount and a motor stator. The gear-up segment is rotatably mounted between the gear disks and has three transmission shafts, three planet gear wheels and multiple bearings. The hub device is mounted around the tubes between the mounting boards and has two hub disks and a hub ring. The hub ring has a spacing disk and two side rings. The electromotor is connected to the gearing device and has a base, a coil stator, an eccentric flywheel, a fan and a protecting hood.

Abstract: A method for forming shallow trench isolation structures is disclosed. The methods include providing a substrate having an upper surface and having an opening extending down from said upper surface, providing a first dielectric layer over at least a portion of the upper surface of the substrate and filling the opening, providing a second dielectric layer over the first dielectric layer, and removing portions of the first and second dielectric layers, wherein the first dielectric layer has a higher index of refraction than the second dielectric layer.

Abstract: A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form a trench. An oxide liner and a nitride liner are then formed in the trench. Subsequently, a two-stage high-density plasma chemical vapor deposition process is performed to form a shallow trench isolation region.

Abstract: The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.

Abstract: The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.