Patents by Inventor Chen-Wei Tsai
Chen-Wei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11982860Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a fixed portion, a movable portion, an electromagnetic driving assembly and an elastic member. The fixed portion has a base and a frame that is disposed on the base. The movable portion is movable relative to the fixed portion, and includes a carrier for carrying an optical member with an incident optical axis. The carrier includes a body and a sidewall that extends along the edge of the body, wherein the carrier further includes a first stopping portion and a second stopping portion protruding towards the fixed portion. The electromagnetic driving assembly drives the movable portion to move relative to the fixed portion. The movable portion is movably connected to the fixed portion via the elastic member.Type: GrantFiled: April 8, 2022Date of Patent: May 14, 2024Assignee: TDK TAIWAN CORP.Inventors: Chia-Che Wu, Sung-Mao Tsai, Chao-Chang Hu, Che-Wei Chang, Chen-Hsien Fan, Chih-Wei Weng
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Publication number: 20240153896Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20240153916Abstract: A semiconductor device includes a bottom semiconductor die including a bottom semiconductor die sidewall, a top semiconductor die bonded to the bottom semiconductor die and including a top semiconductor die sidewall, and a molding material layer formed on an upper surface of the bottom semiconductor die, on the top semiconductor die sidewall, and on the bottom semiconductor die sidewall. A method of forming a semiconductor device includes mounting a bottom semiconductor die including a bottom semiconductor die sidewall on a carrier substrate, mounting a top semiconductor die including a top semiconductor die sidewall on the bottom semiconductor die, and forming a molding material layer on an upper surface of the bottom semiconductor die, on the top semiconductor die sidewall, and on the bottom semiconductor die sidewall.Type: ApplicationFiled: April 21, 2023Publication date: May 9, 2024Inventors: Tsung-Fu TSAI, Chen-Hua YU, Szu-Wei LU
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Publication number: 20240131538Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.Type: ApplicationFiled: December 8, 2022Publication date: April 25, 2024Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
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Publication number: 20240133421Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.Type: ApplicationFiled: January 17, 2023Publication date: April 25, 2024Inventors: Chih-Wei KUO, Yu-Chun HUNG, Che-Yen CHOU, Chen-Wei TSAI, Hsiang-Wen HUANG
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Publication number: 20240134167Abstract: An optical path folding element includes a main body, a light absorption film layer and a matte structure. The main body has optical surface including an incident surface, a reflective surface and an emitting surface. A light enters into the optical folding element through the incident surface. The reflective surface reflects the light so as to change a traveling direction thereof. The light exits the optical folding element through the emitting surface. The light absorbing film layer is configured to reduce reflectance and provided adjacent to at least part of the optical surface, and the light absorbing film layer is in physical contact with the main body. The matte structure is disposed adjacent to at least part of the optical surface. The matte structure provides an undulating profile on a surface of the optical path folding element, and the matte structure is formed in one-piece with the main body.Type: ApplicationFiled: September 24, 2023Publication date: April 25, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Ssu-Hsin LIU, Chen Wei FAN, Chien-Hsun WU, Wen-Yu TSAI, Ming-Ta CHOU
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Publication number: 20240114703Abstract: A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.Type: ApplicationFiled: February 2, 2023Publication date: April 4, 2024Inventors: Tsung-Fu TSAI, Szu-Wei LU, Shih-Peng TAI, Chen-Hua YU
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Publication number: 20240105629Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
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Publication number: 20240099154Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: UNITED MICROELECTRONICS CORPInventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11929314Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: GrantFiled: March 12, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Patent number: 11193933Abstract: The present invention is related to a method for risk detection, diagnosis, prognosis and monitoring of Alzheimer's disease (AD). The method comprises the steps of: (1) measuring the level of glyceraldehyde 3-phosphate dehydrogenase (GAPDH) in a sample from the subject, and (2) comparing the level of GAPDH in the sample with two or more AD reference levels of GAPDH.Type: GrantFiled: October 26, 2016Date of Patent: December 7, 2021Assignee: DR. POWER STEM BIOMEDICAL RESEARCH INC., LTD.Inventors: Chai-Ching Lin, Chen-Wei Tsai
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Patent number: 11075239Abstract: An optical element comprising a transparent substrate and an anti-reflective coating, wherein the anti-reflective coating further comprises at least a transparent, high refractive index layer and a transparent, low refractive index layer, wherein the high refractive index layer is in contact with the low refractive index layer; and wherein the high refractive index layer is situated at an interface between the anti-reflective coating and air. Further, the low refractive index layer may be silicon oxide; the high refractive index layer may be tantalum oxide or silicon nitride.Type: GrantFiled: March 12, 2020Date of Patent: July 27, 2021Assignee: OmniVision Technologies, Inc.Inventors: Chun-Sheng Fan, Chen-Wei Tsai, Wei-Feng Lin
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Publication number: 20200335534Abstract: An optical element comprising a transparent substrate and an anti-reflective coating, wherein the anti-reflective coating further comprises at least a transparent, high refractive index layer and a transparent, low refractive index layer, wherein the high refractive index layer is in contact with the low refractive index layer; and wherein the high refractive index layer is situated at an interface between the anti-reflective coating and air. Further, the low refractive index layer may be silicon oxide; the high refractive index layer may be tantalum oxide or silicon nitride.Type: ApplicationFiled: March 12, 2020Publication date: October 22, 2020Applicant: OmniVision Technologies, Inc.Inventors: Chun-Sheng Fan, Chen-Wei Tsai, Wei-Feng Lin
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Patent number: 10644048Abstract: An optical element comprising a transparent substrate and an anti-reflective coating, wherein the anti-reflective coating further comprises at least a transparent, high refractive index layer and a transparent, low refractive index layer, wherein the high refractive index layer is in contact with the low refractive index layer; and wherein the high refractive index layer is situated at an interface between the anti-reflective coating and air. Further, the low refractive index layer may be silicon oxide; the high refractive index layer may be tantalum oxide or silicon nitride.Type: GrantFiled: February 1, 2017Date of Patent: May 5, 2020Assignee: OmniVision Technologies, Inc.Inventors: Chun-Sheng Fan, Chen-Wei Tsai, Wei-Feng Lin
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Patent number: 10256266Abstract: A chip-scale image sensor package includes a semiconductor substrate, a transparent substrate, a thin film, and a plurality of conductive pads. The semiconductor substrate has (i) a pixel array, and (ii) a peripheral region surrounding the pixel array. The transparent substrate covers the pixel array, has a bottom substrate surface proximate the pixel array, and a top substrate surface opposite the bottom substrate surface. The thin film is on a region of the top substrate surface directly above both (i) the entire pixel array and (ii) a portion of the peripheral region adjacent to the pixel array. Each of the plurality of conductive pads is located within the peripheral region, and is electrically connected to the pixel array. A portion of each of the plurality of conductive pads is not directly beneath the thin film.Type: GrantFiled: April 5, 2017Date of Patent: April 9, 2019Assignee: OmniVision Technologies, Inc.Inventors: Chen-Wei Tsai, Chun-Sheng Fan, Wei-Feng Lin
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Publication number: 20180294298Abstract: A chip-scale image sensor package includes a semiconductor substrate, a transparent substrate, a thin film, and a plurality of conductive pads. The semiconductor substrate has (i) a pixel array, and (ii) a peripheral region surrounding the pixel array. The transparent substrate covers the pixel array, has a bottom substrate surface proximate the pixel array, and a top substrate surface opposite the bottom substrate surface. The thin film is on a region of the top substrate surface directly above both (i) the entire pixel array and (ii) a portion of the peripheral region adjacent to the pixel array. Each of the plurality of conductive pads is located within the peripheral region, and is electrically connected to the pixel array. A portion of each of the plurality of conductive pads is not directly beneath the thin film.Type: ApplicationFiled: April 5, 2017Publication date: October 11, 2018Inventors: Chen-Wei TSAI, Chun-Sheng FAN, Wei-Feng LIN
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Publication number: 20180219034Abstract: An optical element comprising a transparent substrate and an anti-reflective coating, wherein the anti-reflective coating further comprises at least a transparent, high refractive index layer and a transparent, low refractive index layer, wherein the high refractive index layer is in contact with the low refractive index layer; and wherein the high refractive index layer is situated at an interface between the anti-reflective coating and air. Further, the low refractive index layer may be silicon oxide; the high refractive index layer may be tantalum oxide or silicon nitride.Type: ApplicationFiled: February 1, 2017Publication date: August 2, 2018Inventors: Chun-Sheng Fan, Chen-Wei Tsai, Wei-Feng Lin
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Publication number: 20180113129Abstract: The present invention is related to a method for risk detection, diagnosis, prognosis and monitoring of Alzheimer's disease (AD). The method comprises the steps of: (1) measuring the level of glyceraldehyde 3-phosphate dehydrogenase (GAPDH) in a sample from the subject, and (2) comparing the level of GAPDH in the sample with two or more AD reference levels of GAPDH.Type: ApplicationFiled: October 26, 2016Publication date: April 26, 2018Applicant: Dr. Power Stem BiomedicaI Research Inc., Ltd.Inventors: Chai-Ching LIN, Chen-Wei TSAI