Patents by Inventor Chen Wen Huang
Chen Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176093Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Publication number: 20240156092Abstract: The invention relates to a composition for promoting the growth of legumes. The composition includes auxin, choline chloride and ?-aminobutyric acid (GABA). The invention also relates to a method for promoting the growth of legumes.Type: ApplicationFiled: October 26, 2022Publication date: May 16, 2024Inventors: Ting-Wen CHENG, Cho-Chun HUANG, Gui-Jun Li, Kai XIA, Chen-Pang WU
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Publication number: 20240162317Abstract: A non-volatile memory device includes a memory cell including a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes a lateral tip laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric layer covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate, and includes a second thickness (T2). The erase gate covers the erase gate dielectric layer and the lateral tip of the planar floating gate. The first thickness and the second thickness satisfy the following relation: (T2)<(T1)<2(T2).Type: ApplicationFiled: October 20, 2023Publication date: May 16, 2024Inventors: Der-Tsyr Fan, I-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai
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Publication number: 20240133421Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.Type: ApplicationFiled: January 17, 2023Publication date: April 25, 2024Inventors: Chih-Wei KUO, Yu-Chun HUNG, Che-Yen CHOU, Chen-Wei TSAI, Hsiang-Wen HUANG
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Publication number: 20240097035Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20180247886Abstract: The disclosure provides a method for manufacturing an electronic package structure, including disposing on a carrier an electronic component and a conductive frame including a plurality of conductive pads and supporting parts; and covering the electronic component and the supporting parts of the conductive frame with an encapsulating layer while allowing the conductive pads to be exposed from the encapsulating layer, thereby increasing the efficiency and reducing the cost of manufacturing processes with the design of the conductive frame. The disclosure further provides the electronic package structure as described above.Type: ApplicationFiled: May 9, 2017Publication date: August 30, 2018Inventors: Chih-Hsien Chiu, Tsung-Hsien Tsai, Hsin-Lung Chung, Chen-Wen Huang, Fang-Hsien Shen
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Publication number: 20180063966Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.Type: ApplicationFiled: May 30, 2017Publication date: March 1, 2018Inventors: Chih-Hsien Chiu, Chen-Wen Huang, Hsin-Lung Chung, Wen-Jung Tsai, Jia-Huei Hung, Fu-Tang Huang
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Patent number: 9907186Abstract: An electronic package structure is provided, which includes: a carrier; at least one electronic component and a plurality of conductive elements disposed on the carrier; a metal frame bonded to the conductive elements; and an encapsulant formed on the carrier and the metal frame and encapsulating the electronic component and the conductive elements. The metal frame is exposed from the encapsulant to serve as an electrical contact. As such, instead of using a mold having a particular size corresponding to the electronic package structure as in the prior art, the present disclosure can use a common mold to form the encapsulant, thereby reducing the fabrication cost. The present disclosure further provides a method for fabricating the electronic package structure.Type: GrantFiled: May 30, 2017Date of Patent: February 27, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chih-Hsien Chiu, Chen-Wen Huang, Hsin-Lung Chung, Wen-Jung Tsai, Jia-Huei Hung, Fu-Tang Huang
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Publication number: 20070279263Abstract: A network device communicating with a digital clock supply (DCS), a first network, and a second network, includes an input port, a parsing module, and a synthesis module. The input port receives a digital clock signal from the DCS. The parsing module parses the digital clock signal into a plurality of digital clock signals with different frequencies. The synthesis module uses the digital clock signals to synthesize a new digital clock signal. Phase of the new digital clock signal is the same as that of the digital clock signal from the DCS.Type: ApplicationFiled: May 23, 2007Publication date: December 6, 2007Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Tsung-hsi Lee, Chen-wen Huang
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Patent number: 6856207Abstract: A jitter-less phase detector in a clock recovery circuit is disclosed. A first control signal generating circuit generates a first control signal by inverting and delaying input data signals through half clock. A second control signal generating circuit generates a high level second control signal when the data signal changes. A phase comparator generates an up signal having a high-level from the falling edge of the first control signal to the falling edge of the second control signal, and generates a down signal having a high-level from the falling edge of the second control signal to the falling edge of the first control signal, so as to control a pair of current sources to selectively discharge and charge a capacitor.Type: GrantFiled: July 29, 2003Date of Patent: February 15, 2005Assignee: Sunplus Technology Co., Ltd.Inventor: Chen Wen Huang