Patents by Inventor Chen Xie

Chen Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230283462
    Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments balance execution of various iterations in a way that is balanced for different secret values, significantly reducing vulnerability of ladder computations to adversarial side-channel attacks.
    Type: Application
    Filed: March 29, 2022
    Publication date: September 7, 2023
    Inventors: Shuai Wang, Chen Yao, Xiao Wu, Rongzhe Zhu, Yuji Qian, Kun Yang, Weiping Pan, Xixi Xie
  • Publication number: 20230244445
    Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as Montgomery multiplication with reduced interdependencies, using optimized processing resources.
    Type: Application
    Filed: March 29, 2022
    Publication date: August 3, 2023
    Inventors: Shuai Wang, Chen Yao, Xiao Wu, Yuji Qian, Rongzhe Zhu, Xixi Xie
  • Publication number: 20230244482
    Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engines.
    Type: Application
    Filed: March 29, 2022
    Publication date: August 3, 2023
    Inventors: Shuai Wang, Chen Yao, Xiao Wu, Rongzhe Zhu, Yuji Qian, Xixi Xie
  • Publication number: 20230246806
    Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments use masking factors that re-blind secret data without exposing the unmasked secret data between iterations of the ladder computations. Some disclosed embodiments use Montgomery multiplication techniques to facilitate secret data masking by efficiently avoiding modular division operations. Disclosed embodiments significantly reduce the vulnerability of ladder computations to adversarial side-channel attacks.
    Type: Application
    Filed: March 29, 2022
    Publication date: August 3, 2023
    Inventors: Shuai Wang, Chen Yao, Xiao Wu, Rongzhe Zhu, Yuji Qian, Kun Yang, Xixi Xie
  • Publication number: 20230235090
    Abstract: Provided are a bispecific antibody and use thereof. The bispecific antibody comprises a B7-H4-targeting antigen-binding domain and a 4-1BB-targeting antigen-binding domain. The bispecific antibody has one or two or three sites for binding to 4-1BB, along with a novel fully human B7-H4 antibody. The bispecific antibody specifically binds to tumor cells by targeting B7-H4, reducing toxicity induced by 4-1BB activation. In addition, the bispecific antibody of the present invention comprises a human Fc fragment, and thus retains the binding of Fc to FcRn and has a longer half-life.
    Type: Application
    Filed: June 29, 2021
    Publication date: July 27, 2023
    Applicant: HARBOUR BIOMED US, INC.
    Inventors: Lei SHI, Chen ZHONG, Xiaodong WU, Yun HE, Fei CHEN, Xiaocheng LV, Jinli XIE, Yiping RONG, Bing HUANG, Fangfang DU, Jianxun ZHAO
  • Publication number: 20230216954
    Abstract: Embodiments include systems and methods for wireless device signaling a network regarding customized ringing signal (CRS) capability and use of such information by the network. Various embodiments may receiving from the network an INVITE message notifying the wireless device of an incoming call, determining whether the INVITE message indicates that the network provides CRS service if the wireless device supports a CRS function, and including an indication in a response to the INVITE that the wireless device supports the CRS function in response to determining that the INVITE message includes an alert information header field indicating that the network provides CRS service. Various embodiments include a network computing device receiving such information and performing negotiations for CRS service with the wireless device only if the wireless device indicates CRS functional capability.
    Type: Application
    Filed: February 13, 2021
    Publication date: July 6, 2023
    Inventors: Chen Chen, Yong XIE, Yong HOU, Yueming TENG, Grace WANG, Carlos Marcelo Dias PAZOS
  • Publication number: 20230215949
    Abstract: A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 6, 2023
    Inventors: Chen Zhang, Junli Wang, Ruilong Xie, Dechao Guo, Sung Dae Suk
  • Publication number: 20230207632
    Abstract: A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 29, 2023
    Inventors: Indira Seshadri, Ruilong Xie, Chen Zhang, Ekmini Anuja De Silva
  • Publication number: 20230202481
    Abstract: Systems, methods, and devices are disclosed for predicting yield behaviors of objects (vehicles, bicycles, pedestrians, etc.) at a location. An autonomous vehicle located at a first road segment connecting to an intersection having a stop sign can detect a first vehicle approaching the intersection from a second road segment connecting to the intersection. Using a model indicating an average yield location and yield time where both are specific to the second road segment connecting to the intersection, the autonomous vehicle can predict that the first vehicle will yield at the average yield location that is specific to the second road segment.
    Type: Application
    Filed: February 28, 2023
    Publication date: June 29, 2023
    Inventors: Zachary Garcia, Chen Xie
  • Publication number: 20230207697
    Abstract: A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Inventors: Ruilong Xie, Junli Wang, Brent A. Anderson, Chen Zhang, Heng Wu, Alexander Reznicek
  • Publication number: 20230205217
    Abstract: Systems, methods, and devices are disclosed for mapping historical information about behaviors of objects (vehicles, bicycles, pedestrians, etc.) at a location. Based on the mapped historical information, a prediction is determined about a behavior of an object proximate to an autonomous vehicle at the location, where the prediction is based on a statistical analysis of the historical information that is applied to the object. One or more behaviors of the AV are affected based on the prediction.
    Type: Application
    Filed: February 28, 2023
    Publication date: June 29, 2023
    Inventors: Chen Xie, Zachary Garcia, Michael Rusignola, Matthew Fox, Nick Tran, Katherine Anne Fotion, Divya Thakur
  • Publication number: 20230197814
    Abstract: Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Ruilong Xie, Chen Zhang, Jingyun Zhang, Carl Radens
  • Publication number: 20230197778
    Abstract: Embodiments herein include semiconductor structures with an active channel stack having an upper field-effect transistor (FET) and a lower FET vertically stacked below the upper FET The semiconductor structure may also include a dummy stub adjacent to the active channel stack, a lower source/drain (S/D) connected to the active channel stack and laterally extended over the dummy stub, and an upper S/D connected to the active channel stack above the lower S/D.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Ruilong Xie, Chen Zhang, Jingyun Zhang, PIETRO MONTANINI
  • Publication number: 20230184556
    Abstract: The subject disclosure relates techniques for evaluating map quality. In some aspects, a process of the disclosed technology includes steps for receiving change data indicating one or more feature discrepancies associated with one or more geographic regions of a digital map, analyzing the change data to determine which of the one or more feature discrepancies resulted in verified updates to the digital map, and generating a quality score for each of the geographic map regions based on the verified updates. Systems and machine-readable media are also provided.
    Type: Application
    Filed: February 7, 2023
    Publication date: June 15, 2023
    Inventors: Chen Xie, Matthew Fox, Brian Joseph Donohue, Kangyuan Niu, Katherine Leung
  • Publication number: 20230187443
    Abstract: A FET channel comprises a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also comprises a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Ruilong Xie, Chen Zhang, Heng Wu, Julien Frougier, Alexander Reznicek
  • Publication number: 20230178651
    Abstract: Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET1 below a top VTFET1, and a bottom VTFET2 below a top VTFET2, and a method of forming a stacked VTFET device are also provided.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Chen Zhang, Ruilong Xie, Lan Yu, Kangguo Cheng
  • Patent number: 11665877
    Abstract: A compact SRAM design in a stacked architecture is provided. Notably, a 6-transistor SRAM bite cell including a bottom device level containing bottom field effect transistors and a top device level, stacked above the bottom device level, containing top field effect transistors of a different conductivity type than the bottom field effect transistors is provided.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Ruilong Xie, Junli Wang, Dechao Guo
  • Patent number: 11654025
    Abstract: A delivery device for an annuloplasty implant is disclosed comprising an outer sheath, a delivery wire being movable within said sheath in a longitudinal direction thereof, a holder being releasably connectable to said implant, said holder being pivotably connected to a distal portion of said delivery wire, wherein said holder is folded inside said outer sheath in a delivery configuration, and wherein said holder is foldable from said delivery configuration to an expanded deployed configuration outside said outer sheath. A system comprising such delivery device and an annuloplasty implant, and a method of delivering such implant is also disclosed.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 23, 2023
    Inventors: Ger O'Carroll, Mark Pugh, Stuart Deane, Chen Xie, Jake O'Regan
  • Patent number: 11604070
    Abstract: Techniques are disclosed for evaluating digital map quality. A process includes steps for receiving change data indicating one or more feature discrepancies associated with one or more geographic regions of a digital map, analyzing the change data to determine which of the one or more feature discrepancies resulted in verified updates to the digital map, and generating a quality score for each of the geographic map regions based on the verified updates. Systems and machine-readable media are also provided.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 14, 2023
    Assignee: GM Cruise Holdings LLC.
    Inventors: Chen Xie, Matthew Fox, Brian Joseph Donohue, Kangyuan Niu, Katherine Leung
  • Publication number: 20230033518
    Abstract: Systems, methods, and computer-readable media are provided for determining operator availability to provide remote assistance to an autonomous vehicle, determining which of a first plurality of routes will provide a positive ride experience based on the operator availability, and selecting a route of the first plurality of routes for a user based on the determining of which of the first plurality of routes will provide a positive ride experience.
    Type: Application
    Filed: October 13, 2022
    Publication date: February 2, 2023
    Inventors: Charles Bruce Matlack, Sarah Rizk, Linsen Chong, Zsolt Parnaki, Chen Xie