Abstract: The present disclosure relates to a socket with a fixing device and a charging cabinet for electric vehicles with the socket. The fixing device includes a connection mechanism, which is provided on one side of a mainbody of the socket and is adapted to releasably connect the socket to a mounting object to which the socket is to be mounted by means of a first fixing member, and a pivot mechanism, which is provided between the other side of the mainbody opposite to the connection mechanism and the mounting object, so that the socket is pivotable relative to the mounting object when released from the mounting object. Through the fixing device for the electric vehicle charging gun socket, the charging gun socket can be easily and quickly fixed on a mounting object, such as a charging cabinet, since the number of required fixing parts is reduced.

Abstract: The present disclosure provides a video generation method and apparatus, a device, and a medium and a product, and relates to the technical field of computers. The method includes: acquiring description information of a target video to be generated; according to the description information of the target video, acquiring, from a video material library, a target clip corresponding to the description information; splicing the target clip with each candidate clip of a plurality of candidate clips in the video material library respectively to obtain a plurality of candidate videos; evaluating a score of each candidate video of the plurality of candidate videos; and generating the target video according to the score of each candidate video of the plurality of candidate videos.

Abstract: A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.

Abstract: A micro-LED chip includes an epitaxial structure, which includes first and second doped type semiconductor layers and an active layer disposed between the first and second doped type semiconductor layers; a light-emitting side of the first doped type semiconductor layer facing away from the active layer is provided with a patterned structure; and an elongated edge a of the micro-LED chip, a thickness b of the micro-LED chip, and a peak-valley height difference c of the patterned structure satisfy: 0.01?b/a?6, and 0.01?c/b?0.3. By designing a structure size and/or a shape of the micro-LED chip combined with designing the peak-valley height difference of the patterned structure to satisfy the condition of 0.01?c/b?0.3, power of laser lift-off operation can be reduced and a process window thereof is enlarged, and light extraction efficiency of the micro-LED chip is achieved. And a display device using the micro-LED chip is provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first nanosheet transistor having a first source/drain (S/D) region; and a second nanosheet transistor on top of the first nanosheet transistor, the second nanosheet transistor having a second S/D region, the second S/D region being separated from the first S/D region by a dielectric cap layer, wherein the first S/D region of the first nanosheet transistor has a substantially flat top surface adjacent to the dielectric cap layer and has at least one vertical edge that is substantially aligned with an edge of the dielectric cap layer. A method of manufacturing the semiconductor structure is also provided.

Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engines.

Abstract: An approach for creating a buried local interconnect around a DDB (double diffusion break) to reduce parasitic capacitance on a semiconductor device is disclosed. The approach utilizes a metal, as the local interconnect, buried in a cavity around the DDB region of a semiconductor substrate. The metal is disposed by two dielectric layers and the substrate. The two dielectric layers are recessed beneath two gate spacers. The buried local interconnect is recessed into the cavity where the top surface of the interconnect is situated below the top surface of the surrounding S/D (source/drain) epi (epitaxy). The metal of the local interconnect can be made from W, Ru or Co.

Abstract: A semiconductor device a first device located on a frontside of a semiconductor substrate. The semiconductor device further includes an inductor located on a backside of the semiconductor substrate and integrated with a first backside metal (BSM) stack. The semiconductor device further includes a first electrical contact located between the frontside and the backside of the semiconductor substrate. A first end of the first electrical contact is connected to the first BSM stack and a second end of the first electrical contact is connected to a first source/drain region of the first device.

Abstract: Provided are a HEK293T cell strain having high dispersibility and a screening method therefor. Specifically, the present application relates to a method for screening a HEK293T cell strain suitable for serum-free suspension culture, a cell strain screened by using the method, and a method for producing a viral vector by using the cell strain.

Abstract: A semiconductor structure is presented including a backside contact of a nanosheet transistor positioned on a silicon (Si) layer of a wafer and a dielectric liner disposed between the backside contact and the Si layer such that the dielectric liner is located below gate spacers of the nanosheet transistor. The backside contact is closer to a backside of the wafer than a frontside of the wafer. The dielectric liner is vertically aligned with the gate spacers and the dielectric liner is vertically aligned with inner spacers of a nanosheet stack of the nanosheet transistor.

Abstract: The present invention provides semiconductor structures. The semiconductor structures may include a peripheral complimentary metal-oxide semiconductor (CMOS) substrate, a first vertical NAND cell on a first side of the CMOS substrate, and a second vertical NAND cell on a second side of the CMOS substrate opposite the first side.

Abstract: An extract from leaves of mulberry is disclosed. The extract has an IC50 value sufficient to inhibit ?-glucosidase I. The extract may comprise 5-40% (w/w) total imino sugars and 20-70% (w/w) total amino acids. The extract may reduce the production of melanin for the treatment of such ailments or diseases caused by pigmentation as freckle, chloasma, striae gravidarum, sensile plaque and melanoma. The extract may also control blood glucose level.

Abstract: The present disclosure relates to the field of photovoltaic technologies. Disclosed are a solar cell and a photovoltaic module. The solar cell includes: an absorption layer; and an energy selective contact layer located on a surface of the absorption layer, the energy selective contact layer having selectivity for electron energy or hole energy, and the material of the energy selective contact layer including a low-dimensional perovskite material. According to the solar cell and the photovoltaic module provided by the present disclosure, a photovoltaic module can be manufactured.

Abstract: A wafer metrology system having a continuous dynamic sampling scheme configured to optimize a sampling rate for AVI of process wafers in an IC fabrication flow based on acceptable quality levels. For a stable process, the process wafers may be sampled at a lower rate without negatively affecting quality control.

Abstract: Semiconductor devices and methods of forming the same include a semiconductor base having a first width. A semiconductor device over the semiconductor base has a second width that is greater than the first width. A power rail is beneath the semiconductor base. A conductive contact extends from a top of the semiconductor device to the power rail.

Abstract: A semiconductor structure is provided that includes a first pair of stacked devices located in a first active device region and a second pair of stacked devices located in a second active device region. Each stacked device of the pair of stacked devices includes a second field effect transistor (FET) stacked over a first FET, and within each active device region the pair of stacked devices is separated by an inter-device dielectric pillar. A local interconnect structure is located in a non-active device region that is positioned between the first and second active device regions. The local interconnect structure can be connected to a back side power rail and a source/drain region of one of the second FETs, or connected to a front side signal line and a source/drain region of one of the first FETs.

Abstract: The present technology can detect potential labeling conflicts made during different labeling tasks when those tasks are checked in to ensure that a map database is free from conflicts that might interrupt publishing of a map. The present technology can determine whether a first labeled version of map portion is based on a most recent version for the map portion that is stored in the map database, and when it is determined that it is not, and there is an intervening version, the present technology can identify differences between the intervening version of the map portion and the first version of the map portion and identify differences between the second version of the map portion and the first version of the map portion. Based on the identified differences, the present technology can determine whether any of those differences are conflicting.

Abstract: Techniques are disclosed for evaluating digital map quality. A process includes steps for receiving change data indicating one or more feature discrepancies associated with one or more geographic regions of a digital map, analyzing the change data to determine which of the one or more feature discrepancies resulted in verified updates to the digital map, and generating a quality score for each of the geographic map regions based on the verified updates. Systems and machine-readable media are also provided.

Abstract: The subject disclosure relates to ways to improve route duration calculations e.g., estimated time of arrival (ETA) approximations, by taking consideration of reroute probabilities along a given vehicle path. In some aspects, the disclosed technology encompasses a process including steps for identifying a route between a first destination to a second destination, determining a reroute likelihood associated with at least one AV maneuver along the route, and calculating an estimated time of arrival (ETA) based on the reroute likelihood associated with at least one AV maneuver. Systems and machine-readable media are also provided.

Abstract: The subject disclosure relates to ways to determine a data collection surveillance cadence. In some aspects, a process of the disclosed technology includes steps for receiving historic map data for one or more geographic regions, wherein each of the one or more geographic regions comprises one or more map features, calculating a change rate for each of the one or more map features, and determining a surveillance cadence for each of the one or more geographic regions based on the change rate for each of the one or more map features. Systems and machine-readable media are also provided.