Abstract: Methods for revitalizing components of a plasma processing apparatus that includes a sensor for detecting a thickness or roughness of a peeling weakness layer on a protective surface coating of a plasma processing tool and/or for detecting airborne contaminants generated by such peeling weakness layer. The method includes detecting detrimental amounts of peeling weakness layer buildup or airborne concentration of atoms or molecules from the peeling weakness layer, and initiating a revitalization process that bead beats the peeling weakness layer to remove it from the component while maintaining the integrity of the protective surface coating.

Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.

Abstract: A system substrate package, a system package, and methods of forming the same are described herein. The system substrate package includes an integrated substrate with multiple discrete interconnect structures. In embodiments the multiple discrete interconnect structures are placed and encapsulated and have a gap formed between the multiple discrete interconnect structures. The system substrate package reduces package warpage and mitigates board level reliability issues.

Abstract: A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein.

Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

Abstract: A semiconductor package and methods of forming the same are disclosed. In an embodiment, a package includes a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.

Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

Abstract: A package includes a package substrate including an insulating layer having a trench and a package component bonded to the package substrate. The package component includes a redistribution structure, an optical die bonded to the redistribution structure, the optical die including an edge coupler near a first sidewall of the optical die, a dam structure on the redistribution structure near the first sidewall of the optical die, a first underfill between the optical die and the redistribution structure, an encapsulant encapsulating the optical die, and an optical glue in physical contact with the first sidewall of the optical die. The first underfill does not extend along the first sidewall of the optical die. The optical glue separates the dam structure from the encapsulant. The package further includes a second underfill between the insulating layer and the package component. The second underfill is partially disposed in the trench.

Abstract: An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.

Abstract: A method includes forming a package, which includes an optical die and a protection layer attached to the optical die. The optical die includes a micro lens, with the protection layer and the micro lens being on a same side of the optical die. The method further includes encapsulating the package in an encapsulant, planarizing the encapsulant to reveal the protection layer, and removing the protection layer to form a recess in the encapsulant. The optical die is underlying the recess, with the micro lens facing the recess.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A photonic assembly includes a composite die. The composite die includes: a photonic integrated circuits (PIC) die including waveguides and photonic devices therein; an electronic integrated circuits (EIC) die including semiconductor devices therein; and an embedded optical connector die contacting a top surface of the PIC die and laterally spaced from the EIC die.

Abstract: A method of fabrication a package and a stencil structure are provided. The stencil structure includes a first carrier having a groove and stencil units placed in the groove of the first carrier. At least one of the stencil units is slidably disposed along sidewalls of another stencil unit. Each of the stencil units has openings.

Abstract: A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.

Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

Abstract: A method for fabricating an optical element is provided. The fabrication method includes the following steps. A substrate is provided. A plurality of first dielectric layers, a plurality of metal layers of Ag or its alloy and a plurality of second dielectric layers are formed over the substrate. The plurality of first dielectric layers and the plurality of metal layers are alternately formed over the substrate. The plurality of second dielectric layers are formed on one side away from the substrate of the plurality of metal layers and located between the plurality of metal layers and the plurality of first dielectric layers. An optical element fabricated by the method is also provided.

Abstract: A display device includes a substrate, gate lines, a driving circuit, and auxiliary gate lines. The substrate has a display area. The gate lines are disposed on the display area, and are in parallel with a first edge of the display area. The gate lines include a first gate line which is farthest from the first edge. The driving circuit is disposed adjacent to the first edge. The auxiliary gate lines substantially perpendicular to the gate lines are connected to the gate lines, and are in parallel with a second edge of the display area. The auxiliary gate lines include a first auxiliary gate line and at least one auxiliary gate line. The first auxiliary gate line is configured to connect the first gate line to the driving circuit. The at least one auxiliary gate line is disposed between the second edge and the first auxiliary gate line.

Abstract: A display device includes a substrate, gate lines, a driving circuit, and auxiliary gate lines. The substrate has a display area. The gate lines are disposed on the display area, and are in parallel with a first edge of the display area. The gate lines include a first gate line which is farthest from the first edge. The driving circuit is disposed adjacent to the first edge. The auxiliary gate lines substantially perpendicular to the gate lines are connected to the gate lines, and are in parallel with a second edge of the display area. The auxiliary gate lines include a first auxiliary gate line and at least one auxiliary gate line. The first auxiliary gate line is configured to connect the first gate line to the driving circuit. The at least one auxiliary gate line is disposed between the second edge and the first auxiliary gate line.