Patents by Inventor CHEN-YING HSU

CHEN-YING HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240196762
    Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Feng Hsu, Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Hengyuan Lee, Xinyu BAO
  • Patent number: 11940659
    Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
  • Patent number: 11944019
    Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Feng Hsu, Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Hengyuan Lee, Xinyu Bao
  • Publication number: 20240074337
    Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. The phase change layer includes a GeSbTe material that contains a Ge content of about 20 at % or less, a Sb content of about 30 at % or more, and a Te content of about 40 at % at or more.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hengyuan Lee, Cheng-Chun Chang, Chen-Feng Hsu, Tung-Ying Lee, Xinyu BAO
  • Publication number: 20230117312
    Abstract: A smart interactive game system includes a host, a display module, an electronic ticket database, a contactless electronic ticket, and a communication module. The host displays an initial interface through the display module, then generates service information according to first choice information of the initial interface. Through the communication module, encryption information related to the contactless electronic ticket is sent to the electronic ticket database to generate electronic ticket information. A virtual and real integrated interface associated with the service information is displayed through the display module. The host generates value-adding and redemption information according to first manipulation of the virtual and real integrated interface, and updates the electronic ticket information and the encryption information according to the value-adding and redemption information.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 20, 2023
    Inventors: REN-JYE CHANG, JY-NING CHANG, CHEN-YING HSU, JIUN-PIN JUNG