Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A deep learning method of an artificial intelligence model for medical image recognition is provided. The method includes the following steps: obtaining a first image set, where the first image set includes at least two images captured with different parameters; performing image pre-processing on each image of the first image set to obtain a second image set; performing image augmentation on the second image set to obtain a third image set; adding the third image set to a training image data set; and training the artificial intelligence model using the training image data set.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: Disclosed are an edge tool configuration method and an electronic device. The edge tool configuration method includes: detecting a placement status of the electronic device through a sensor; reading configuration information of the edge tool according to the placement status, wherein the configuration information includes initial configuration information of the edge tool in a plurality of default placement statuses; placing the edge tool at an edge position in a display interface of a display according to the configuration information in the placement status.

Abstract: An electronic device including a body and a receptacle connector is provided. The body has a side wall surface, a receptacle slot located at the side wall surface, a waterproof protrusion protruding from the side wall surface, and two gutters located at the side wall surface, where the waterproof protrusion is located above the receptacle slot, and the two gutters are respectively located at two opposite sides of the receptacle slot. The receptacle connector is disposed in the receptacle slot.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.

Abstract: A switching power converter includes: a power stage circuit, including at least one transistor which is configured to operably switch an inductor to convert an input power to an output power; and an active EMI filter circuit, including at least one amplifier, wherein the at least one amplifier is configured to operably sense a noise input signal which is related to a switching noise caused by the switching of the power stage circuit, and amplify the noise input signal to generate a noise cancelling signal, wherein the noise cancelling signal is injected into an input node of the switching power converter, so as to suppress the switching noise and thus reducing EMI, wherein the input power is provided through the input node to the power stage circuit.

Abstract: A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A manufacturing control method is applied to a computer system comprising a processor, a storage device, and a display device. The manufacturing control method includes: dividing a plurality of outlier-filtered data into a plurality of data subgroups based on a group division reference value; calculating a plurality of standard deviations for each of these data subgroups; calculating a warning line upper limit and a warning line lower limit based on the group division reference value, a predetermined multiple, and the standard deviations; adjusting either the warning line upper limit or the warning line lower limit based on the predetermined multiple and the standard deviations; and when a sensing data exceeds the warning line upper limit or the warning line lower limit, the computing system triggers a warning signal.

Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Abstract: A device and a method for detecting a light irradiating angle are disclosed. The device, used to detect the incident direction of a light ray, includes a solar sensor and a processor. The sensing unit of the solar sensor has sensing areas. The sensing areas correspondingly generate sensing signals based on the intensity of the light ray. A mask covers the sensing unit and has an X-shaped light transmitting portion. The light ray transmits the X-shaped light transmitting portion to form an X-axis light ray and a Y-axis light ray. The X-axis light ray intersects the Y-axis light ray. The X-axis light ray and the Y-axis light ray fall on the sensing area. The processor, coupled to the sensing unit, receives the sensing signals and determines information of the incident direction according to the sensing signals.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An optical driving mechanism is provided, including a movable portion, a fixed portion, a driving component and a first stopper component. The movable portion is configured to connect an optical element. The movable portion is movable relative to the fixed portion. The driving component is configured to drive the movable portion to move relative to the fixed portion. The first stopper component is configured to limit the range of movement of the movable portion relative to the fixed portion.

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly can include a substrate and one or more semiconductor dies. The semiconductor device assembly can further include a thermally conductive material (e.g., carbon nanotubes, graphene) capable of dissipating heat from the semiconductor device assembly. In doing so, a thermally regulated semiconductor device can be assembled.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate, a plurality of electrical contacts disposed on an outer surface of the substrate, a solder resist disposed on the outer surface of the substrate and including an opening defined by a plurality of edges and exposing the plurality of electrical contacts, and an alpha particle shield disposed proximate to at least one edge, of the plurality of edges.

Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate and a die stack carried by the package substrate. The die stack can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die. The first semiconductor die can have an upper surface and a first bond pad carried by the upper surface that includes a curvilinear concave depression formed in an uppermost surface of the first bond pad. The second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The die stack can also include solder structure electrically coupling the first and second bond pads and at least partially filling the curvilinear concave depression formed in the uppermost surface of the first bond pad.

Abstract: A semiconductor package having a fillet is provided. The semiconductor package includes a trace disposed within a solder mask that has a top surface. A first die is over the solder mask and mechanically couples with the trace. A first adhesive is between the trace and the first die where sides of the first die and the first adhesive define a die edge. The semiconductor package includes a fillet adjacent the die edge and a second die above the first die. The semiconductor package also includes a second adhesive having a bottom surface where the second adhesive is between the first die and the second die. The solder mask top surface, the first die surface, and the second adhesive bottom surface define a cavity where the fillet is within the cavity at the die edge.

Abstract: The disclosure provides a forming method of a halogen-free flame-retardant material. The method includes the followings. A twin-screw extruder including a first zone and a second zone is used. A mixture in the first zone is mixed, melted and heated to form a molten mixture. The mixture includes a halogen-free flame retardant, a wear-resistant modifier, a thermoplastic elastomer, and an antioxidant. In addition, a silane-modified nano-silica aqueous suspension is introduced into the second zone to mix the silane-modified nano-silica aqueous suspension with the molten mixture from the first zone. The first zone and the second zone are continuously connected regions.