Abstract: A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Abstract: Embodiments herein relate to a phase interpolator for interpolating phases of input clock signals. In a series of interpolating cells, each cell receives clock signals having a phase offset between them and outputs an interpolated clock signal having a phase between the phases of the input clock signals. The received clock signals control the on and off time for first and second current sources of the interpolator cell. Additionally, a pulldown transistor is controlled by an internally-generated clock signal from a previous cell in the series, and each cell outputs an internally-generated clock signal that is fed to the next cell in the series to control its pulldown transistor. As a result, the duty cycle of the interpolated clock signal is made constant. A programmable common mode voltage removes any systematic direct current (DC) error in transferring the pulldown signal from one interpolator cell to another.

Abstract: A testing circuit is provided. The testing circuit includes a clock cone, a series of shift register chains, and a control circuit. The clock cone is divided into a plurality of fan-out partitions operated in the same clock domain. The shift register chains are configured to shift out one-hot signals on demand and each shift register chain includes multiple registers with the same amount as fan-out partitions. The control circuit receives the one-hot signals from the shift register chains and enables the divided fan-out partitions therefore.

Abstract: A display panel has a plurality of pixel areas and a peripheral area surrounding the pixel areas, and includes a substrate, at least two planarization layers, a plurality of pads, a first dummy pattern, and a plurality of light-emitting devices. The substrate has a first substrate edge extending in a first direction. The at least two planarization layers are disposed on the substrate. The pads are disposed on the at least two planarization layers, and are located in the pixel areas. The pads include at least one first edge pad closest to the first substrate edge. The first dummy pattern is disposed on the at least two planarization layers, and extends in the peripheral area between the at least one first edge pad and the first substrate edge. The light-emitting devices are electrically connected to the pads.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A method of identifying defects in crystals includes the following steps. A silicon carbide crystal to be identified for defects is sliced to obtain a test piece. An etching process is performed on the test piece. Etching conditions of the etching process includes the following. An etchant including potassium hydroxide is used, and etching is performed at a temperature of 400° C. to 550° C. in an environment where dry air or oxygen is introduced, so as to form etching pits of threading edge dislocations (TED) and threading screw dislocations (TSD) in the test piece. After the etching process is performed, a diameter ratio (TED/TSD) of the etching pits of the threading edge dislocations (TED) and the threading screw dislocations (TSD) observed by an optical microscope in the test piece is in a range of 0.2 to 0.5.

Abstract: A modular AC/DC power conversion module for power sources and loads and a method of driving the same is provided. When an AC/DC converter is electrically coupled to an external power source, a microprocessor is electrically energized by a buck auxiliary circuit, under control of the microprocessor, a DC/DC converter is activated for a certain time period, and then, the AC/DC converter is activated. Thereafter, an output voltage of the AC/DC converter is boosted, and an output voltage of the DC/DC converter is boosted accordingly. Power elements in the downstream side DC/DC converter are activated first, and then power elements in the upstream side AC/DC converter are activated, thereby an inrush current is suppressed. Once the external power source is connected, the buck auxiliary circuit will automatically reduce a voltage of the power input to activate the module. It realizes that the module will autonomously operate after being electrically energized.

Abstract: A system includes a plurality of network access devices that are remotely distributed and coupled to at least one Internet-coupled, wide-area wireless network. Each of the plurality of network access devices persistently execute respective device management programs. The device management programs are operable to read and change local device status and maintain respective persistent network socket connections. The system includes an Internet-coupled data center with one or more servers that operate a plurality of Simple Network Management Protocol (SNMP) agent programs. Each of the SNMP agent programs communicate with a respective one of the device management programs via the persistent network socket connections. The SNMP agent programs provide an SNMP interface at the data center. A network management station manages the respective network access devices via the respective SNMP interfaces, the respective device management programs, and the respective persistent network socket connections.

Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A semiconductor device includes a gate structure, a first doped region, a second doped region, an isolation structure, an insulating layer and a field plate. The gate structure is located on a substrate. The first doped region and the second doped region are located at two sides of the gate structure. The isolation structure is located in the substrate between the first doped region and the second doped region, and is separated from the gate structure by a non-zero distance. The insulating layer extends continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure. The field plate is located on the insulating layer and has the same potential as the gate structure.

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.

Abstract: The present invention provides a sensor circuit with noise elimination comprising: a reference circuit which receives plural first sensing signals and generates a ramp signal based on the first sensing signal; and a comparison circuit which is coupled to the reference circuit, and which receives a second sensing signal and a ramp signal and generates a count signal based on the ramp signal and the second sensing signal and records the count signal at the time when the ramp signal is equal to the second sensing signal, thereby eliminating the noise of the second sensing signal to obtain a noise-free sensing value. The count signal is recorded when the ramp signal and the second sense signal are equal, so that the noise of the second sense signal is eliminated and a noise-free sense value is obtained.