Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, and a conductive filler. The polymer matrix has a fluoropolymer. The total volume of the PTC material layer is calculated as 100%, and the fluoropolymer accounts for 47-62% by volume of the PTC material layer. The fluoropolymer has a melt viscosity higher than 3000 Pa·s.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a first conductive filler. The polymer matrix includes a polyolefin-based polymer and a fluoropolymer. The fluoropolymer has a melt flow index higher than 1.9 g/10 min, and the polyolefin-based polymer and the fluoropolymer together form an interpenetrating polymer network (IPN). The first conductive filler has a metal-ceramic compound dispersed in the polymer matrix.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.

Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of an input voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: The present invention discloses a receive data equalization apparatus. A delay-compensating calculation circuit retrieves training data groups of a training data signal to retrieve total delay amount, generate signed compensation amounts according to a relation among training data contents of training data in each of the training data groups to generate total compensation amount accordingly, and solve equations that correspond total delay amount of the training data groups to the total compensation amount to obtain each of the compensation amounts. A receive data equalization circuit receives the compensation amounts and retrieves a receive data group in a receive data signal, generate signed receive compensation amounts according to a relation among receive data contents of receive data in the receive data group to generate a total receive compensation amount accordingly to perform equalization on a terminal edge of the receive data group according to the total receive compensation amount.

Abstract: The present invention discloses a receive data equalization apparatus. A delay-compensating calculation circuit retrieves training data groups of a training data signal to retrieve total delay amount, generate signed compensation amounts according to a relation among training data contents of training data in each of the training data groups to generate total compensation amount accordingly, and solve equations that correspond total delay amount of the training data groups to the total compensation amount to obtain each of the compensation amounts. A receive data equalization circuit receives the compensation amounts and retrieves a receive data group in a receive data signal, generate signed receive compensation amounts according to a relation among receive data contents of receive data in the receive data group to generate a total receive compensation amount accordingly to perform equalization on a terminal edge of the receive data group according to the total receive compensation amount.

Abstract: The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.

Abstract: The invention discloses a low voltage differential signal (LVDS) receiver, which is realized in an integrated circuit. The LVDS receiver includes: an input stage circuit receiving a full-range common-mode voltage and converting it into a current signal; a current source circuit coupled to the input stage circuit to provide a current source; and a current mirror circuit coupled the input stage circuit and the current source circuit to provide several bias voltage signals for the current source circuit and output a voltage signal to a buffer.