Patents by Inventor Chenchen Jacob WANG

Chenchen Jacob WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12022664
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Lin Chen, Chenchen Jacob Wang, Hsin-Wen Su, Ping-Wei Wang, Yuan-Hao Chang, Po-Sheng Lu, Shih-Hao Lin
  • Patent number: 12002534
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chenchen Jacob Wang, Yi-Ching Liu, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin, Yih Wang
  • Publication number: 20240172433
    Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chih-Yu CHANG, Han-Jong CHIA, Chenchen Jacob WANG, Yu-Ming LIN
  • Patent number: 11991887
    Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chenchen Jacob Wang, Chun-Chieh Lu, Yi-Ching Liu
  • Publication number: 20240099025
    Abstract: A memory device includes at least one bit line, at least one word line, at least one memory cell, at least one source line, and a controller electrically coupled to the at least one memory cell via the at least one word line, the at least one bit line, and the at least one source line. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, and first and second source/drains. Each data storage element and the corresponding second transistor are electrically coupled in series with the first source/drain of the first transistor and the bit line. The controller controllably applies a voltage other than a ground voltage to the at least one source line in an operation of a selected data storage element among the data storage elements.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Meng-Han LIN, Sai-Hooi YEONG, Han-Jong CHIA, Chenchen Jacob WANG, Yu-Ming LIN
  • Publication number: 20240090236
    Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Han-Jong CHIA, Bo-Feng YOUNG, Sai-Hooi YEONG, Chenchen Jacob WANG, Meng-Han LIN, Yu-Ming LIN
  • Patent number: 11903189
    Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
  • Patent number: 11864393
    Abstract: A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each of the select bit lines is electrically coupled to a gate of a corresponding second transistor. Each data storage element and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line. The controller turns ON the first transistor and a selected second transistor, and, while the first transistor and the selected second transistor are turned ON, applies different voltages to the bit line to perform corresponding different operations on the data storage element coupled to the selected second transistor.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Sai-Hooi Yeong, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
  • Patent number: 11864392
    Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Han-Jong Chia, Bo-Feng Young, Sai-Hooi Yeong, Chenchen Jacob Wang, Meng-Han Lin, Yu-Ming Lin
  • Publication number: 20230389336
    Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chenchen Jacob Wang, Sai-Hooi Yeong, Yu-Ming Lin, Chi On Chui
  • Publication number: 20230345736
    Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Chenchen Jacob Wang, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Sai-Hooi Yeong
  • Patent number: 11729994
    Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 15, 2023
    Inventors: Chenchen Jacob Wang, Yu-Ming Lin, Chi On Chui, Sai-Hooi Yeong, Bo-Feng Young
  • Publication number: 20230157034
    Abstract: A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each of the select bit lines is electrically coupled to a gate of a corresponding second transistor. Each data storage element and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line. The controller turns ON the first transistor and a selected second transistor, and, while the first transistor and the selected second transistor are turned ON, applies different voltages to the bit line to perform corresponding different operations on the data storage element coupled to the selected second transistor.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 18, 2023
    Inventors: Meng-Han LIN, Sai-Hooi YEONG, Han-Jong CHIA, Chenchen Jacob WANG, Yu-Ming LIN
  • Patent number: 11631698
    Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Han-Jong Chia, Chenchen Jacob Wang
  • Patent number: 11581368
    Abstract: A memory device includes at least one bit line, at least one word line, and at least one memory cell. The memory cell includes a first transistor, a plurality of data storage elements, and a plurality of second transistors corresponding to the plurality of data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each data storage element among the plurality of data storage elements and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Sai-Hooi Yeong, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
  • Patent number: 11581336
    Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Ming Lin, Chun-Chieh Lu, Bo-Feng Young, Han-Jong Chia, Chenchen Jacob Wang, Sai-Hooi Yeong
  • Patent number: 11574928
    Abstract: A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chenchen Jacob Wang, Sai-Hooi Yeong, Bo-Feng Young, Chun-Chieh Lu, Yu-Ming Lin
  • Patent number: 11563006
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a front end of line (FEOL) structure, and a metallization structure. The FEOL structure is disposed over the substrate. The metallization structure is over the FEOL structure. The metallization structure includes a transistor structure, an isolation structure, and a capacitor. The transistor structure has a source region and a drain region connected by a channel structure. The isolation structure is over the transistor structure and exposing a portion of the source region, and a side of the isolation structure has at least a lateral recess vertically overlaps the channel structure. The capacitor is in contact with the source region and disposed conformal to the lateral recess. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sai-Hooi Yeong, Chenchen Jacob Wang, Yu-Ming Lin
  • Patent number: 11527542
    Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Chi On Chui, Chenchen Jacob Wang
  • Publication number: 20220384483
    Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Han-Jong Chia, Chenchen Jacob Wang