Abstract: A sense amplifier latch (SAL) provides complimentary outputs in a reset phase to feed them directly to the Decision Feedback Equalizer (DFE) taps from SAL soft decision (d1x & d1xb) to improve the performance of DFE first tap 1-UI (one unit-interval) critical timing. The latch generates the complimentary resetting values on differential outputs in reset time. The latch enables in the required time i.e., once evaluation is done it shuts the current sinking path. The latch can extrapolate to rail-to-rail input common mode range of operation.

Abstract: Apparatus for managing high speed Universal Serial Bus 2.0 (USB2) communications is presented. The apparatus may include a combination differential difference detector to receive first and second input signals, the combination differential difference detector to, in a first mode: sense a first voltage difference between the first and second input signals and output a squelch signal when the first voltage difference is less than or equal to a pre-defined value. The combination differential difference detector is to, in a second mode, sense a second voltage difference between the first and second input signals and output a disconnect signal when the second voltage difference is greater than or equal to a pre-defined value. Related methods may also be disclosed.

Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.

Abstract: A method and system implements a repeater in a link of a communication medium. The method and system enables a counter to count alternations of a clock signal received from a host or device over the link, compares a value of the counter to a reference count, adjusts a frequency selection based on the comparison of the value of the counter to the reference count, and locks the frequency selection in response to the counter matching the reference count.

Abstract: An apparatus is provided, where the apparatus includes a transmitter comprising a first stage and a second stage, wherein the first stage is to receive an input voltage and generate bias for the second stage, and wherein the second stage comprises a driver circuitry to transmit data using the bias voltage; and a control circuitry to control generation of the bias, based on receiving a feedback of the input voltage.

Abstract: An apparatus is provided, where the apparatus includes a transmitter comprising a first stage and a second stage, wherein the first stage is to receive an input voltage and generate bias for the second stage, and wherein the second stage comprises a driver circuitry to transmit data using the bias voltage; and a control circuitry to control generation of the bias, based on receiving a feedback of the input voltage.

Abstract: A microelectronic assembly may include a first microelectronic device, a second microelectronic device, a first signal link, a second signal link, and a first power connection. The first microelectronic device may include a first interface powered at a first voltage. The second microelectronic device may include a second interface powered at a second voltage. The first signal link may supply a first signal at the first voltage from the first interface to the second interface. The second signal link may supply a second signal at the second voltage from the second interface to the first interface. The first power connection may supply a first reference signal at the first voltage from the first interface to the second interface.

Abstract: An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

Abstract: An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.

Abstract: Apparatus for managing high speed Universal Serial Bus 2.0 (USB2) communications is presented. The apparatus may include a combination differential difference detector to receive first and second input signals, the combination differential difference detector to, in a first mode: sense a first voltage difference between the first and second input signals and output a squelch signal when the first voltage difference is less than or equal to a pre-defined value. The combination differential difference detector is to, in a second mode, sense a second voltage difference between the first and second input signals and output a disconnect signal when the second voltage difference is greater than or equal to a pre-defined value. Related methods may also be disclosed.

Abstract: A microelectronic assembly may include a first microelectronic device, a second microelectronic device, a first signal link, a second signal link, and a first power connection. The first microelectronic device may include a first interface powered at a first voltage. The second microelectronic device may include a second interface powered at a second voltage. The first signal link may supply a first signal at the first voltage from the first interface to the second interface. The second signal link may supply a second signal at the second voltage from the second interface to the first interface. The first power connection may supply a first reference signal at the first voltage from the first interface to the second interface.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.

Abstract: A method and system implements a repeater in a link of a communication medium. The method and system enables a counter to count alternations of a clock signal received from a host or device over the link, compares a value of the counter to a reference count, adjusts a frequency selection based on the comparison of the value of the counter to the reference count, and locks the frequency selection in response to the counter matching the reference count.

Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.

Abstract: In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal.

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.