Patents by Inventor Cheng-An Lin
Cheng-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12232326Abstract: A memory device includes a first conductive via, a first conductive line, an etch stop layer, a plurality of stacks and a first conductive pillar. The first conductive line is disposed on and in physical contact with the first conductive via. The etch stop layer is disposed on and in physical contact with the first conductive line. The stacks are disposed on the etch stop layer. The first conductive pillar is disposed between the stacks. The first conductive pillar extends between opposite surfaces of the stacks to be in physical contact with the first conductive line.Type: GrantFiled: January 10, 2022Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Feng-Cheng Yang
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Patent number: 12230545Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: GrantFiled: November 30, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Patent number: 12227759Abstract: A temperature-sensitive cell culture composition is provided. The temperature-sensitive cell culture composition includes a hydrogel, a cellulose, a gelatin and a collagen. Based on 1 part by weight of the collagen, a content of the hydrogel is between 0.03 parts by weight and 60 parts by weight, a content of the cellulose is between 150 parts by weight and 360 parts by weight, and a content of the gelatin is between 21 parts by weight and 12 parts by weight. In addition, a method for using the temperature-sensitive cell culture composition, a method for forming the temperature-sensitive cell culture composition, and a use of the temperature-sensitive cell culture composition are also provided.Type: GrantFiled: December 18, 2020Date of Patent: February 18, 2025Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chia-Jung Lu, Jing-En Huang, Liang-Cheng Su, Hsin-Hsin Shen, Yuchi Wang, Ying-Hsueh Chao, Li-Hsin Lin, Hsiu-Hua Huang
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Patent number: 12230554Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.Type: GrantFiled: July 27, 2023Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Wei-Tao Tsai
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Patent number: 12230323Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.Type: GrantFiled: April 20, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
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Patent number: 12225973Abstract: A method for manufacturing a recycled carbon fiber underlay, which mixes recycled carbon fiber material with nylon or composite plastic and forms an elastic recycled carbon fiber injection particle material, and under an injection process condition, the recycled carbon fiber injection particle material is injected and molded into a recycled carbon fiber underlay. The recycled carbon fiber arch insole comprises a recycled carbon fiber underlay manufactured by the aforementioned manufacturing method, together with the data of podiatric medical big numeric database of human factors engineering for the innovative design of mechanical insole products and the application development of recycled materials to encourage recycling to reduce carbon emissions, while improving the function, durability, and comfort of insole inserts.Type: GrantFiled: February 13, 2023Date of Patent: February 18, 2025Assignee: DR. FOOT TECHNOLOGY CO., LTD.Inventor: Wei-Cheng Lin
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Patent number: 12232322Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.Type: GrantFiled: October 30, 2023Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chen Wang, Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia
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Patent number: 12230537Abstract: A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions.Type: GrantFiled: August 4, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Ya Lo, Cheng-Chin Lee, Shao-Kuan Lee, Chi-Lin Teng, Hsin-Yen Huang, Hsiaokang Chang, Shau-Lin Shue
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Patent number: 12230744Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,Type: GrantFiled: September 20, 2023Date of Patent: February 18, 2025Assignee: EPISTAR CORPORATIONInventors: Chao-Hsing Chen, Cheng-Lin Lu, Chih-Hao Chen, Chi-Shiang Hsu, I-Lun Ma, Meng-Hsiang Hong, Hsin-Ying Wang, Kuo-Ching Hung, Yi-Hung Lin
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Patent number: 12227619Abstract: The present invention provides a polyimide-based copolymer and electronic component and field effect transistor comprising the same. The polyimide-based copolymer comprises a copolymer of dianhydride and heterocyclic diamine, wherein the heterocyclic diamine has two benzene rings, and there are two ether bonds, two thioether bonds, or one ether bond and one thioether bond between the two benzene rings. The novel polyimide-based copolymer of the invention has excellent thermal-mechanical stability, has potential application prospects, and can be used as a substrate for flexible electronics.Type: GrantFiled: June 11, 2021Date of Patent: February 18, 2025Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Wen-Chang Chen, Mitsuru Ueda, Chun-Kai Chen, Yan-Cheng Lin
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Patent number: 12230320Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.Type: GrantFiled: June 16, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
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Patent number: 12230645Abstract: A stretchable pixel array substrate, including a base and a component layer, is provided. The base has multiple first openings and multiple second openings. Each of the first openings has a first opening extending direction. Each of the second openings has a second opening extending direction. The first opening extending direction and the second opening extending direction are different. The first openings and the second openings are alternately arranged in a first direction and a second direction to define multiple islands and multiple bridges of the base. The component layer is disposed on the base and includes multiple island portions and multiple bridge portions. The island potions have multiple pixel structures and are respectively disposed on the islands of the base. The bridge portions have conductive wires and are respectively disposed on the bridges of the base. The conductive wires are electrically connected to the pixel structures.Type: GrantFiled: July 29, 2021Date of Patent: February 18, 2025Assignee: Au Optronics CorporationInventors: Yun-Wen Pan, Kung-Cheng Lin
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Publication number: 20250054662Abstract: The present invention relates to a thermistor paste and a manufacturing method thereof. The thermistor paste includes specific contents of thermistor powder, a glass powder, and an organic carrier, in which the organic carrier includes an organic solvent, a binder, and an additive. A thermistor semi-finished product slurry of the present invention has been sintered. The thermistor paste of the present invention excludes a precious metal, such as ruthenium, gold, or platinum, etc., so the production cost can be reduced.Type: ApplicationFiled: November 27, 2023Publication date: February 13, 2025Inventors: Shen-Li HSIAO, Kuang-Cheng LIN, Wei-Chen HUANG, Ren-Hong WANG
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Publication number: 20250054536Abstract: A memory device includes a memory array, a first reference voltage circuit, a first read voltage control circuit and a first write voltage control circuit. The first reference voltage circuit is configured to provide a first reference voltage signal having a first voltage level to the memory array. The first read voltage control circuit is configured to adjust the first reference voltage signal to a second voltage level when the memory array is read. The first write voltage control circuit is configured to adjust the first reference voltage signal to a third voltage level when the memory array is written. The second voltage level is higher than the first voltage level, and the third voltage level is lower than the first voltage level.Type: ApplicationFiled: August 11, 2023Publication date: February 13, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Tao CHOU, Hsin-Cheng LIN, Jih-Chao CHIU, Chee-Wee LIU
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Publication number: 20250056782Abstract: A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.Type: ApplicationFiled: August 10, 2023Publication date: February 13, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung UniversityInventors: Tao CHOU, Hsin-Cheng LIN, Ching-Wang YAO, Li-Kai WANG, Chee-Wee LIU, Chenming HU
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Publication number: 20250056819Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.Type: ApplicationFiled: January 2, 2024Publication date: February 13, 2025Inventors: Wei-Lun Chung, Chung-Lei Chen, Anhao Cheng, Chien-Wei Lee, Yen-Liang Lin, Ru-Shang Hsiao
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Publication number: 20250056851Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.Type: ApplicationFiled: October 28, 2024Publication date: February 13, 2025Inventors: Jen-Hong Chang, Yi-Hsiu Liu, You-Ting Lin, Chih-Chung Chang, Kuo-Yi Chao, Jiun-Ming Kuo, Yuan-Ching Peng, Sung-En Lin, Chia-Cheng Chao, Chung-Ting Ko
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Publication number: 20250055188Abstract: A Reconfigurable ReflectArray (RRA) structure includes a P-Intrinsic-N (P-I-N) diode and a metal circuit. The metal circuit includes a first metal member and a second metal member. The first metal member is coupled to one end of the P-I-N diode. The second metal member is coupled to another end of the P-I-N diode. One of the first metal member and the second metal member includes a first radiating portion and a second radiating portion. The first radiating portion is located between the P-I-N diode and the second radiating portion. The first radiating portion has a first length. The second radiating portion has a second length. The first length is different from the second length.Type: ApplicationFiled: February 1, 2024Publication date: February 13, 2025Inventors: Shih-Cheng LIN, Sheng-Fuh CHANG, Chia-Chan CHANG, Yuan-Chun LIN, Ting-Hao SHIN
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Publication number: 20250051467Abstract: An FAP/CD40 binding molecule and the medicinal use thereof. Specifically, provided are an FAP binding molecule, a CD40 binding molecule and an FAP/CD40 binding molecule, a method for preventing and treating diseases (such as tumors or cancers) using same, and the medicinal use thereof.Type: ApplicationFiled: August 24, 2022Publication date: February 13, 2025Inventors: Yuan Lin, Simeng Chen, Tingting Wu, Rongting Hu, Cheng Liao
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Patent number: D1062545Type: GrantFiled: May 7, 2023Date of Patent: February 18, 2025Assignees: Acer Incorporated, Acer Gadget Inc.Inventors: Yun Cheng, Ker-Wei Lin, Hao-Ming Chang, Chun-Ta Chen, Wei-Chen Lee, Chih-Yuan Chang