Abstract: A chamber adaptor and a manufacturing method thereof. The chamber adaptor includes: a housing provided with a gas inlet, a gas outlet, a chamber inlet, and a chamber outlet, where the gas inlet is configured to be removably connected to a main board device, the gas outlet is configured to be removably connected to a respiratory pathway, the chamber inlet is configured to be removably connected to an input end of a chamber for storing liquid and the chamber outlet is configured to be removably connected to an output end of the chamber, the chamber adaptor further includes a control circuit and at least one sensing apparatus, where the at least one sensing apparatus is arranged on one end of the control circuit closer to the gas outlet and extends into a gas output channel.

Abstract: A terminal, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: receiving an object in a live streaming; displaying the object on the terminal; detecting a keyword in the object corresponding to a function in the live streaming; and triggering the function in response to an operation on the object. The present disclosure may allow the streamers to generate or amend an object such as stickers on the live streaming room in a more flexible manner. At the same time, the viewer may perform an operation on the object to realize a corresponding function in a more convenient manner. Therefore, the interaction among streamers and viewers may be increased, and the user experience may also be enhanced.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A calculation system for predicting a proppant embedding depth based on a shale softening effect is provided, including a sampling test terminal, a scheduling module, a monitoring module, and a calculation module, wherein the scheduling module, the monitoring module, and the calculation module are connected in communication, and the monitoring module is connected to an external operating system through a wireless network, wherein the external operating system is configured to perform a hydraulic fracturing operation and receive a first control signal and/or a second control signal from the monitoring module. The sampling test terminal is configured to test the samples and obtain test data. The scheduling module is configured to determine a target construction parameter.

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.

Abstract: The present disclosure provides a method for preparing lithium iron phosphate from ferric hydroxyphosphate, including: purifying ferrous sulfate to form a ferrous sulfate solution, adding hydrogen peroxide, phosphoric acid, an ammonium dihydrogen phosphate solution and ammonia water into the ferrous sulfate solution and then reacting to form a mixed slurry, holding the mixed slurry at a temperature for a period of time, and then washing with water and subjecting to press filtration to form ferric hydroxyphosphate precursors with different iron-phosphorus ratios; then flash drying, sintering at a high temperature, and pulverizing to obtain ferric hydroxyphosphate precursors with different iron-phosphorus ratios and different specific surface areas.

Abstract: Provided are an audio/video processing method and apparatus, a device, and a storage medium. The method comprises: displaying text data corresponding to an audio/video to be edited, wherein the text data has a mapping relation with an audio/video timestamp of said audio/video; displaying said audio/video according to a time axis track; in response to a preset operation triggered for target text data in the text data, determining an audio/video timestamp corresponding to the target text data as a target audio/video timestamp; and processing, on the basis of the preset operation, an audio/video clip corresponding to the target audio/video timestamp in said audio/video.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: A display panel includes a gate electrode, a source electrode, a drain electrode, and a metal oxide layer disposed corresponding to the gate electrode. The metal oxide layer includes a lower metal oxide layer and an upper metal oxide layer stacked on the lower metal oxide layer. The lower metal oxide layer includes an indium oxide and a lanthanoid oxide. The upper metal oxide layer is located on a surface of the lower metal oxide layer adjacent to the source electrode and the drain electrode. The source electrode and the drain electrode are connected to the upper metal oxide layer. The upper metal oxide layer includes an indium oxide and a lanthanoid oxide, and the upper metal oxide layer includes polycrystalline phase.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: One or more embodiments of the present specification provide a method and device for capacity degradation prediction of a lithium-ion battery. The method comprises the following steps: acquiring an original battery discharge capacity; decomposing the original battery discharge capacity through a predetermined mode decomposition method to obtain battery discharge capacities composed of a plurality of different frequency signals; inputting the respective frequency signals into a pre-constructed capacity prediction model to obtain capacity prediction results corresponding to the respective frequency signals; selecting capacity prediction result that satisfies a predetermined relevance condition corresponding to the respective frequency signals; and reconstructing the finally predicted battery discharge capacity according to the capacity prediction result that satisfies the predetermined relevance condition.

Abstract: The application discloses a correction method, correction device and correction system for free full-screen splicing. According to the application, influence of reasons such as an external light source and a camera angle is eliminated based on curved surface simulation over color information data of multiple pixels, so that free full splicing may be implemented when a spliced display screen, after being used, is disassembled and transferred to another site for re-splicing.

Abstract: A method for protecting a power system having inverter-interfaced renewable energy sources is provided. The power system includes an inverter and a control system. The control system includes a current controller including a saturation limiter and a proportional and integral (PI) controller, a phase-locked system, and a low-voltage ride-through (LVRT)control unit. The method includes: by using a Park transformation matrix, determining an output voltage of the inverter; determining a modulated voltage of the output voltage; upon detecting a grid fault, obtaining current references by the LVRT control unit; determining a fault current in a first stage of a transient phase of the grid fault; determining a fault current in a second stage of the transient phase; determining a fault current in a third stage of the transient phase; and switching the control system to a fault control mode by tracking the fault currents in the first, second and third stages, to the current references.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.