Abstract: A computing device and a data access method therefor are provided. The computing device includes a bus, a destination memory circuit, and a source memory circuit. The source memory circuit provides multiple pieces of data to the destination memory circuit through the bus based on a burst access instruction. In an embodiment, a source address in the burst access instruction is one of multiple consecutive addresses of a source memory, and a destination address in the burst access instruction is a virtual address. In another embodiment, a source address in the burst access instruction is a virtual address, and a destination address in the burst access instruction is one of multiple consecutive addresses in the destination memory circuit. In yet another embodiment, a source address in the burst access instruction is a first virtual address, and a destination address in the burst access instruction is a second virtual address.