Patents by Inventor Cheng C. Shih

Cheng C. Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5249183
    Abstract: A local area network (LAN) having a 10Base-T media attachment unit (MAU) is disclosed for coupling an attachment unit interface (AUI) to a twisted pair link through an AUI port of the 10Base-T MAU. In addition to meeting or exceeding standards set forth in the proposed supplement (P802.3I/D10) to IEEE standard 802.3 for LANs, the MAU provides an interface between the AUI and a RJ45 (twisted pair) connector which auto-engages when activity is detected on the twisted pair link. Lack of activity on the twisted pair link forces the 10Base-T MAU to isolate its AUI port from the AUI. An Ethernet (coaxial) type MAU commonly connected with the 10Base-T MAU at the AUI may be utilized without manual intervention when the twisted pair link is inactive.
    Type: Grant
    Filed: March 14, 1991
    Date of Patent: September 28, 1993
    Assignee: Level One Communications, Inc.
    Inventors: Dave Wong, Haim Shafir, Joe Heideman, Cheng C. Shih
  • Patent number: 5166635
    Abstract: A cost-effective, low power and low distortion digital data line driver is disclosed with the capability to operate from a limited voltage source while maintaining wide output voltage swings. The line driver has the noise immunity attribute of a fully differential input device without all the usual complex CMFB circuitry normally required. The line driver provides a low distortion output with a low output impedance and maintains its impedance value on the same order of magnitude at frequencies up to four times the Nyquist rate.
    Type: Grant
    Filed: March 27, 1991
    Date of Patent: November 24, 1992
    Assignee: Level One Communications, Inc.
    Inventor: Cheng C. Shih
  • Patent number: 5057794
    Abstract: An all-digital phase-locked loop (ADPLL) is disclosed having a wide bandwidth while maintaining relatively small steps for phase error correction. A random walk filter with memory and a pattern sensitive phase adjustment circuit cooperate to control the ADPLL frequency/phase adjustment rate by taking multiple, relatively smnall steps in phase error correction at fixed intervals of time. A short cycle occurs when the phase disparity is large, interrupting the execution of the fixed interval cycle expediting the ADPLL phase lock time without sacrificing resolution in the phase error correction steps.
    Type: Grant
    Filed: February 26, 1991
    Date of Patent: October 15, 1991
    Assignee: Level One Communications, Inc.
    Inventor: Cheng C. Shih