Abstract: An integrated circuit comprising a plurality MAC processors, interconnected into a linear pipeline, configurable to process input data, wherein each MAC processor includes (A) a multiplier and (B) an accumulator circuit, and (C) a plurality of rotate input data paths, wherein each rotate input data path couples two sequential MAC processors of the linear pipeline including an input of the multiplier circuit of a first MAC processor of sequential MAC processors to an input of the multiplier circuit of the immediately following MAC processor of the associated sequential MAC processors of the pipeline—wherein each rotate input data path is configurable to provide rotate input data from a first MAC processor of sequential MAC processors of the linear pipeline to the immediately following MAC processor of the associated sequential MAC processors thereby forming a serial circular path via the plurality of rotate input data paths.

Abstract: An integrated circuit comprising a plurality of multiplier-accumulator circuits connected in series to form a linear pipeline to process first data, via performing a plurality of concatenated multiply and accumulate operations, and generate MAC output data, wherein each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits includes (i) a multiplier to multiply first data by a multiplier weight data and generate a product data, and (ii) an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second data and the product data of the associated multiplier to generate sum data. The integrated circuit further includes an activation circuit, connected to the output of the linear pipeline of the plurality of multiplier-accumulator circuits, to receive the MAC output data and process the MAC output data, via a non-linear activation function, to generate MAC pipeline output data.

Abstract: An integrated circuit comprising a plurality of MACs, connected to form a pipeline, to perform a plurality of multiply and accumulate operations, wherein each MAC includes: (A) a multiplier, coupled to memory to (i) receive the multiplier weight data, (ii) multiply first data and the multiplier weight data and (iii) output product data, (B) an accumulator, coupled to the multiplier of the MAC, to add second data and the first product data and output sum data, and (C) a load-store register, coupled to: (i) an output of the accumulator of the associated MAC and (ii) an input of the load-store register of an immediately successive MAC. Each load-store register may include two interconnected registers, and is configurable to, on the same clock cycle, (a) load the initialization data into the accumulator of the immediately successive MAC and (b) store the sum data from the associated MAC into the load-store register.

Abstract: An integrated circuit including a multiplier-accumulator circuit pipeline including a plurality of MAC circuits. Each MAC circuit includes: (A) a multiplier circuit to multiply first input data and filter weight data to generate and output first product data having a floating point data format, and (B) a coarse floating point accumulator circuit including: (1) an alignment shift circuit to shift at least one field of the first product data and generate shifted first product data, and (2) fixed point addition circuitry, coupled to the alignment shift circuit, to add second input data and the shifted first product data using the fixed point addition circuitry. The plurality of MAC circuits of the multiplier-accumulator circuit execution pipeline, in operation, each perform a plurality of multiply operations and accumulate operations to process the first input data and generate processed data therefrom.

Abstract: An integrated circuit comprising a plurality MAC pipelines wherein each MAC pipeline includes: (i) a plurality of MACs connected in series and (ii) a plurality of data paths including an accumulation data path, wherein each MAC includes a multiplier to multiply to generate product data and an accumulator to generate sum data. The integrated circuit further comprises a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with a MAC pipeline, wherein each control/configure circuit includes an accumulation data path which is configurable to directly connect to the accumulation data path of the MAC pipeline to form an accumulation ring when the control/configure circuit is configured in an accumulation mode, and an output data path configurable to directly connect to the output of the accumulation data path of the MAC pipeline when the control/configure circuit is configured in an output data mode.

Abstract: Multiply-accumulate processors within a tensor processing unit simultaneously execute, in each of a sequence of multiply-accumulate cycles, respective complex-data multiply operations using a shared complex data operand and respective fast-Fourier-transform parameters, each of the multiply-accumulate processors applying a new complex input data operand and respective fast-Fourier-transform parameter in each successive multiply-accumulate cycle to accumulate, as a component of a resultant fast Fourier transform, a respective sum of complex multiplication products.

Abstract: A system and/or an integrated circuit including: (a) a multiplier-accumulator execution pipeline including multiplier-accumulator circuits to process image data, using associated filter weights, via a plurality of multiply and accumulate operations and (b) first data format conversion circuitry including (i) inputs to receive filter weights of a plurality of sets of filter weights, wherein each set includes a plurality of filter weights each having a block-scaled fraction data format, (ii) conversion circuitry, coupled to the inputs, to convert the filter weights of each set from the block-scaled fraction data format to a floating point data format, and (iii) outputs to output the filter weights having the floating point data format. In operation, the multiplier-accumulator circuits of the pipeline are configured to perform the plurality of multiply and accumulate operations using (a) the image data and (b) the filter weights having the floating point data format.

Abstract: An integrated circuit including a multiplier-accumulator execution pipeline including a plurality of multiplier-accumulator circuits to process the data, using filter weights, via a plurality of multiply and accumulate operations. The integrated circuit includes first conversion circuitry, coupled the pipeline, having inputs to receive a plurality of sets of data, wherein each set of data includes a plurality of data, Winograd conversion circuitry to convert each set of data to a corresponding Winograd set of data, floating point format conversion circuitry, coupled to the Winograd conversion circuitry, to convert the data of each Winograd set of data to a floating point data format. In operation, the multiplier-accumulator circuits are configured to perform the plurality of multiply and accumulate operations using the data of the plurality of Winograd sets of data from the first conversion circuitry and the filter weights, and generate output data based on the multiply and accumulate operations.

Abstract: An integrated circuit including a plurality of processing components to process image data of a plurality of image frames, wherein each image frame includes a plurality of stages. Each processing component includes a plurality of execution pipelines, wherein each pipeline includes a plurality of multiplier-accumulator circuits configurable to perform multiply and accumulate operations using image data and filter weights, wherein: (i) a first processing component is configurable to process all of the data associated with a first plurality of stages of each image frame, and (ii) a second processing component of the plurality of processing components is configurable to process all of the data associated with a second plurality of stages of each image frame. The first and second processing component processes data associated with the first and second plurality of stages, respectively, of a first image frame concurrently.

Abstract: An integrated circuit device includes a broadcast data path, a weighting-value memory, Winograd conversion circuitry and multiply-accumulate units. The Winograd conversion circuitry executes a first Winograd conversion function with respect to an input data set to render a converted input data set onto the broadcast data path and executes a second Winograd conversion function with respect to a filter-weight data set to store a converted weighting data set within the weighting-value memory. The multiply-accumulate units, coupled in common to the broadcast data path to receive the converted input data set and coupled to receive respective converted weighting data values from the weighting-value memory, execute a parallel sequence of multiply-accumulate operations to generate an interim output data set that is, in turn, converted to a final output data set through execution of a third Winograd conversion function within the Winograd conversion circuitry.

Abstract: An integrated circuit device includes operand storage circuitry to output first and second operands each having a first standard floating point format, multiplier circuitry to multiply the first and second operands to generate a multiplication product first having a second standard floating point format and product accumulation circuitry. The product accumulation circuitry reformats the multiplication product to coarse floating format having a reduced numeric range relative to the originally generated multiplication product and then adds the reformatted multiplication product to a previously generated accumulation value, also having the coarse floating point format, to generate an updated accumulation value having the coarse floating point format, storing the updated accumulation value in place of the previously generated accumulation value.

Abstract: A floating-point summation circuit implemented within an integrated circuit device and having inputs to receive a first normalized floating-point operand having an exponent field and a fraction field, and a non-normalized floating-point operand having an exponent field and a fraction field, the fraction field of the non-normalized floating-point operand having a first significant bit in any of at least two different bit positions. Normalizing circuitry within the floating-point summation circuit generates, at least by normalizing the fraction field of the non-normalized floating-point operand, a second normalized floating-point operand having a value corresponding to that of the non-normalized floating point operand, and adder circuitry within the floating-point summation-circuit generates a floating-point sum by adding the first and second normalized floating-point operands.

Abstract: An integrated circuit device includes one or more broadcast data paths, a weighting-value memory and multiply-accumulate (MAC) units. The MAC units are coupled in common to each of the broadcast data paths and coupled to receive respective weighting values from the weighting-value memory via respective weighting-value paths. Each of the MAC units includes MAC circuits that each receive an input data value via a respective one of the broadcast data paths and a shared one of the weighting values via a shared one of the respective weighting-value paths; generate a sequence of multiplication products by multiplying the input data value with the shared one of the weighting values; and accumulate a sum of the multiplication products. A configuration value stored within a programmable register controls the number of timing cycles over which the sum of the multiplication products is accumulated.

Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.

Abstract: An integrated circuit including a plurality of processing components to process image data of a plurality of image frames, wherein each image frame includes a plurality of stages. Each processing component includes a plurality of execution pipelines, wherein each pipeline includes a plurality of multiplier-accumulator circuits configurable to perform multiply and accumulate operations using image data and filter weights, wherein: (i) a first processing component is configured to process all of the data associated with a first plurality of stages of each image frame, and (ii) a second processing component of the plurality of processing components is configured to process all of the data associated with a second plurality of stages of each image frame. The first and second processing component processes data associated with the first and second plurality of stages, respectively, of a first image frame concurrently.

Abstract: An integrated circuit device includes broadcast data paths, a weighting-value memory, multiply-accumulate (MAC) units, and shared shift-out circuitry. The MAC units are coupled in common to each of the broadcast data paths and coupled to receive respective weighting values from the weighting-value memory via respective weighting-value paths. Each of the MAC units includes MAC circuits that each receive an input data value via a respective one of the broadcast data paths and a shared one of the weighting values via a shared one of the respective weighting-value paths; generate a sequence of multiplication products by multiplying the input data value with the shared one of the weighting values; accumulate a sum of the multiplication products; and output the sum of the multiplication products to a respective one of a plurality of serially coupled storage elements within the shared shift-out path.

Abstract: An integrated circuit device includes broadcast data paths, a weighting-value memory, multiply-accumulate (MAC) units, and shared shift-out circuitry. The MAC units are coupled in common to each of the broadcast data paths and coupled to receive respective weighting values from the weighting-value memory via respective weighting-value paths. Each of the MAC units includes MAC circuits that each receive an input data value via a respective one of the broadcast data paths and a shared one of the weighting values via a shared one of the respective weighting-value paths; generate a sequence of multiplication products by multiplying the input data value with the shared one of the weighting values; accumulate a sum of the multiplication products; and output the sum of the multiplication products to a respective one of a plurality of serially coupled storage elements within the shared shift-out path.

Abstract: An integrated circuit including control/configure circuitry which interfaces with a plurality of interconnected MACs and/or one or more rows of interconnected connected MACs. The control/configure circuitry may include a plurality of control/configure circuits, each control/configure circuit interfaces with at least one MAC pipeline, wherein each pipeline includes a plurality of linearly connected multiplier-accumulator circuits. Each control/configure circuit may include one or more of (i) a configurable input data signal path to provide data to the MACs of the pipeline during the execution sequence(s) and (ii) a configurable output data path for the output data generated by execution sequence (i.e., input data that was processed via the multiplier-accumulator circuits of the pipeline).

Abstract: An integrated circuit device includes broadcast data paths, a weighting-value memory, and multiply-accumulate (MAC) units. The MAC units are coupled in common to each of the broadcast data paths and coupled to receive respective weighting values from the weighting-value memory via respective weighting-value paths. Each of the MAC units includes a plurality of MAC circuits coupled respectively to the broadcast data paths, with each of the MAC circuits within a given one of the MAC units (i) receiving an input data value via a respective one of the broadcast data paths and a shared one of the weighting values via a shared one of the respective weighting-value paths, (ii) generating a sequence of multiplication products by multiplying the input data value with the shared one of the weighting values, and (iii) accumulating a sum of the multiplication products.

Abstract: An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.