Abstract: An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high temperature drive-in and oxidation cycle with a 1000-2500 .ANG. thick nitride mask covering device areas. The floating gate stack is formed by forming a first gate oxide layer depositing a first polysilicon layer having a thickness of 2000-2600 .ANG., removing these layers from non-memory cell areas, growing a uniformly thick second oxide layer at 1100.degree.-1200.degree. C.