Patents by Inventor Cheng Chang
Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979158Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.Type: GrantFiled: May 26, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yu Lin, Yung-Chen Chien, Jia-Hong Gao, Jerry Chang Jui Kao, Hui-Zhong Zhuang
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Patent number: 11980037Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.Type: GrantFiled: June 19, 2020Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Jack T. Kavalieros, Uygar E. Avci, Chia-Ching Lin, Seung Hoon Sung, Ashish Verma Penumatcha, Ian A. Young, Devin R. Merrill, Matthew V. Metz, I-Cheng Tung
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Publication number: 20240145596Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
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Publication number: 20240144467Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Publication number: 20240145304Abstract: An interconnect structure is provided. The interconnect structure includes a transistor on a substrate, a first dielectric layer over the transistor, a first metal line through the first dielectric layer, a second dielectric layer over the first dielectric layer, and a via through the second dielectric layer and on the first metal line. A first side surface of the first dielectric layer includes a first portion in direct contact with the first metal line and a second portion in direct contact with the via, and the first portion of the first side surface of the first dielectric layer is aligned with the second portion of the first side surface of the first dielectric layer.Type: ApplicationFiled: December 22, 2023Publication date: May 2, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Han LIN, Che-Cheng CHANG
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Publication number: 20240143141Abstract: The present disclosure generally relates to underwater user interfaces.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Benjamin W. BYLENOK, Alan AN, Richard J. BLANCO, Andrew CHEN, Maxime CHEVRETON, Kyle B. CRUZ, Walton FONG, Ki Myung LEE, Sung Chang LEE, Cheng-I LIN, Kenneth H. MAHAN, Anya PRASITTHIPAYONG, Alyssa RAMDYAL, Eric SHI, Xuefeng WANG, Wei Guang WU
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Publication number: 20240145389Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.Type: ApplicationFiled: July 28, 2023Publication date: May 2, 2024Inventors: Li-Chiu WENG, Yew Teck TIEO, Ming-Hsuan WANG, Chia-Cheng CHEN, Wei-Yi CHANG, Jen-Hang YANG, Chien-Hsiung HSU
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Publication number: 20240140742Abstract: A detecting method of a sheet detection device includes: generating, by a first magnetic sensing element, a first voltage signal corresponding to a magnetic element; generating, by a second magnetic sensing element, a second voltage signal corresponding to the magnetic element; determining, by a processing element, a first relative position of the magnetic element relative to the first magnetic sensing element according to the first voltage signal; determining, by the processing element, a second relative position of the magnetic element relative to the second magnetic sensing element according to the second voltage signal; determining, by the processing element, a stopping position of the magnetic element according to the first relative position and the second relative position; determining, by the processing element, a paper size of a paper abutted by a paper guide according to the stopping position. A sheet detection device is also disclosed.Type: ApplicationFiled: December 6, 2022Publication date: May 2, 2024Inventors: Tzu-Cheng CHANG, Wei-Chun JAU
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Publication number: 20240142361Abstract: There is provided a smoke detector including a substrate, a light source and a light sensor. The light source and the light sensor are arranged adjacently on the substrate. The substrate is arranged with an asymmetric structure to cause an illumination region of the light source to deviate toward the light sensor thereby increasing a ratio of light intensity reflected by smoke with respect to reference light intensity.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: YEN-CHANG CHU, CHENG-NAN TSAI, CHIH-MING SUN
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Patent number: 11971657Abstract: A photoresist developer includes a solvent having Hansen solubility parameters of 15<?d<25, 10<?p<25, and 6<?p<30; an acid having an acid dissociation constant, pKa, of ?15<pKa<4, or a base having a pKa of 40>pKa>9.5; and a chelate.Type: GrantFiled: April 11, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang, Yahru Cheng
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Patent number: 11973040Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.Type: GrantFiled: December 9, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
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Patent number: 11973302Abstract: The present disclosure provides a method for aligning a master oscillator power amplifier (MOPA) system. The method includes ramping up a pumping power input into a laser amplifier chain of the MOPA system until the pumping power input reaches an operational pumping power input level; adjusting a seed laser power output of a seed laser of the MOPA system until the seed laser power output is at a first level below an operational seed laser power output level; and performing a first optical alignment process to the MOPA system while the pumping power input is at the operational pumping power input level, the seed laser power output is at the first level, and the MOPA system reaches a steady operational thermal state.Type: GrantFiled: February 20, 2023Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Lin Louis Chang, Henry Tong Yee Shian, Alan Tu, Han-Lung Chang, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
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Publication number: 20240132904Abstract: The present invention relates to a method for producing recombinant human prethrombin-2 protein and having human ?-thrombin activity by the plant-based expression systems.Type: ApplicationFiled: October 16, 2023Publication date: April 25, 2024Applicant: PROVIEW-MBD BIOTECH CO., LTD.Inventors: Yu-Chia CHANG, Jer-Cheng KUO, Ruey-Chih SU, Li-Kun HUANG, Ya-Yun LIAO, Ching-I LEE, Shao-Kang HUNG
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Publication number: 20240132621Abstract: Disclosed herein an isolated neutralizing antibody, which is capable of specifically binding to chitinase-3-like protein-1 (YKL-40) and uses thereof. The neutralizing antibody can further conjugate with a metal chelator to form an antibody complex. Further, labeling the antibody complex with a radioactive metal nuclide results in formation of a radioactive antibody complex, which can be used as a contrast agent and treatment for YKL-40 over-expression-related diseases. The radioactive antibody complex can specifically bind to YKL-40, and can be used for diagnosis and the preparation of the use of the treatment for cancers related to YKL-40 over-expression.Type: ApplicationFiled: April 18, 2023Publication date: April 25, 2024Inventors: Ming-Cheng Chang, Ping-Fang Chiang, Yu-Jen Kuo
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Publication number: 20240133481Abstract: A tank valve system comprises a main valve body, an overfill protection device (OPD), a gauge drive apparatus and a fuel level indicator. The OPD and gauge drive apparatus are configured to both be inserted through a narrow neck of a fuel storage tank prior to connecting the valve body to the neck. The valve body includes a primary fuel channel and a shuttle interface channel. The OPD includes an overfill float driving an overfill shutoff valve for controlling fluid flow from the primary channel into the tank. The gauge drive apparatus includes a gauge float, a shuttle, and an elongated extension body. The gauge float is movable with respect to the extension body between an uppermost position and a lowermost position, thereby driving the shuttle. The shuttle has a gauge actuation portion transportable within the shuttle interface channel to thereby actuate the fuel level indicator.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Shmuel Dovid Newman, Chin-Cheng Chang
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Publication number: 20240135745Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: InnnoLux CorporationInventors: Kuei-Sheng Chang, Po-Yang Chen, Kuo-Jung Wu, I-An Yao, Wei-Cheng Lee, Hsien-Wen Huang
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Publication number: 20240136946Abstract: This patent presents a multidimensional space vector modulation (MDSVM) circuit formed by coupling a half-bridge logic control circuit not directly coupled to electronic components with at least three half-bridge logic control circuits coupled to electronic components. The half-bridge logic control circuit not directly coupled with any electronic components can form a full-bridge circuit with any other half-bridge logic control circuit coupled with electronic components. Therefore, users can further control the voltage difference between both ends of each electronic component separately and then individually control the strength and direction of current flowing through each electronic component and solving the problem of control attributed to the complexity of prior art.Type: ApplicationFiled: April 10, 2023Publication date: April 25, 2024Applicant: TENSOR TECH CO., LTDInventors: Shang Jung LEE, Po-Hsun YEN, Yung-Cheng CHANG, Sung-Liang HOU
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Publication number: 20240136428Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
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Patent number: 11967594Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: GrantFiled: August 10, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240127765Abstract: Disclosed are a display device and a backlight control method for the display device. The display device includes a display panel, a backlight source, a first computing unit, and a second computing unit. The display panel includes a first display region and a second display region. The first light-emitting region corresponds to the first display region. The second light-emitting region corresponds to the second display region. The first computing unit calculates a first brightness distribution within a first range. The second computing unit calculates a second brightness distribution within a second range. The first light-emitting region emits light according to the first brightness distribution. The second light-emitting region emits light according to the second brightness distribution.Type: ApplicationFiled: September 11, 2023Publication date: April 18, 2024Applicants: Innolux Corporation, CARUX TECHNOLOGY PTE. LTD.Inventors: Yi-Cheng Chang, Yu-Ming Wu