Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: A solar cell and a manufacturing method thereof are provided. A laser doping process is adopted to form positive and negative doping regions for an accurate control of the doping regions. No metal contact coverage issue arises since a contact opening is formed by later firing process. The solar cell is provided with a comb-like first electrode, a sheet-like second electrode corresponding to the doping regions to obtain high photoelectric conversion efficiency by fully utilizing the space in the semiconductor substrate. Furthermore, the sheet-like second electrode can be formed by a material having high reflectivity to improve the light utilization rate of the solar cell. The manufacturing process of the solar cell is simplified and the processing yield is improved.

Abstract: A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.

Abstract: A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.

Abstract: A solar cell and a manufacturing method thereof are provided. A laser doping process is adopted to form positive and negative doping regions for an accurate control of the doping regions. No metal contact coverage issue arises since a contact opening is formed by later firing process. The solar cell is provided with a comb-like first electrode, a sheet-like second electrode corresponding to the doping regions to obtain high photoelectric conversion efficiency by fully utilizing the space in the semiconductor substrate. Furthermore, the sheet-like second electrode can be formed by a material having high reflectivity to improve the light utilization rate of the solar cell. The manufacturing process of the solar cell is simplified and the processing yield is improved.

Abstract: An LTPS-TFT structure comprises a gate, a gate dielectric layer, a patterned silicon layer, a patterned insulating layer, an ohmic contact layer and a source/drain layer. The gate and the gate dielectric layer are disposed on the substrate. The patterned silicon layer and the patterned insulating layer are disposed on the gate dielectric layer over the gate. The patterned silicon layer comprises a polysilicon channel region and an amorphous silicon hot carrier restrain region. The ohmic contact layer is disposed on a portion of the patterned silicon layer other than the polysilicon channel region and the amorphous silicon hot carrier restrain region and a portion of the patterned insulating layer over the amorphous silicon hot carrier restrain region. The source/drain layer is disposed on the ohmic contact layer and the gate dielectric layer.

Abstract: An LTPS-TFT structure comprises a gate, a gate dielectric layer, a patterned silicon layer, a patterned insulating layer, an ohmic contact layer and a source/drain layer. The gate and the gate dielectric layer are disposed on the substrate. The patterned silicon layer and the patterned insulating layer are disposed on the gate dielectric layer over the gate. The patterned silicon layer comprises a polysilicon channel region and an amorphous silicon hot carrier restrain region. The ohmic contact layer is disposed on a portion of the patterned silicon layer other than the polysilicon channel region and the amorphous silicon hot carrier restrain region and a portion of the patterned insulating layer over the amorphous silicon hot carrier restrain region. The source/drain layer is disposed on the ohmic contact layer and the gate dielectric layer.

Abstract: A LTPS-TFT structure comprising a cap layer, a polysilicon film and a gate is provided. The cap layer is disposed over the substrate with a gap between the two. The polysilicon film is disposed over the cap layer and is divided into a channel region and a source/drain region on each side of the channel region. The channel region is located above the gap. The gate is disposed above the channel region. Because the gap lies underneath the channel region, the thermal conductivity in the channel region is lower during the laser annealing process. Therefore, the silicon atoms can have a longer re-crystallization time so that larger grains are formed within the channel region and grain boundary therein is reduced. Furthermore, the grain orientation of the polysilicon film is mostly parallel to the transmission direction of electron within the transistor so that the operation efficiency of the transistor is improved.

Abstract: A LTPS-TFT structure comprising a cap layer, a polysilicon film and a gate is provided. The cap layer is disposed over the substrate with a gap between the two. The polysilicon film is disposed over the cap layer and is divided into a channel region and a source/drain region on each side of the channel region. The channel region is located above the gap. The gate is disposed above the channel region. Because the gap lies underneath the channel region, the thermal conductivity in the channel region is lower during the laser annealing process. Therefore, the silicon atoms can have a longer re-crystallization time so that larger grains are formed within the channel region and grain boundary therein is reduced. Furthermore, the grain orientation of the polysilicon film is mostly parallel to the transmission direction of electron within the transistor so that the operation efficiency of the transistor is improved.

Abstract: An LTPS-TFT structure comprises a gate, a gate dielectric layer, a patterned silicon layer, a patterned insulating layer, an ohmic contact layer and a source/drain layer. The gate and the gate dielectric layer are disposed on the substrate. The patterned silicon layer and the patterned insulating layer are disposed on the gate dielectric layer over the gate. The patterned silicon layer comprises a polysilicon channel region and an amorphous silicon hot carrier restrain region. The ohmic contact layer is disposed on a portion of the patterned silicon layer other than the polysilicon channel region and the amorphous silicon hot carrier restrain region and a portion of the patterned insulating layer over the amorphous silicon hot carrier restrain region. The source/drain layer is disposed on the ohmic contact layer and the gate dielectric layer.