Patents by Inventor Cheng-Chao Lin

Cheng-Chao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200149572
    Abstract: A connector structure includes a connector body which has an end provided with an enlarged stop portion which is provided with a connecting section which has a diameter smaller than that of the connector body. The connecting section is provided with a recess which is formed between the enlarged stop portion and the connector body. In assembly, each of the connector bodies is initially inserted into the entrance of each of the steel angles, the connecting section of each of the connector bodies is then moved downward and inserted into the locking hole of each of the steel angles, and the recess of each of the connector bodies is then locked onto the inner wall and the outer wall of each of the steel angles, such that each of the connector bodies is secured to each of the steel angles.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 14, 2020
    Inventor: Cheng-Chao Lin
  • Patent number: 7205634
    Abstract: An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: April 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Miao-Cheng Liao, Kuo-Hsien Cheng, Cheng-Chao Lin, Shao-Ta Hsu, Ying-Lang Wang
  • Publication number: 20050202616
    Abstract: An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.
    Type: Application
    Filed: March 10, 2004
    Publication date: September 15, 2005
    Inventors: Miao-Cheng Liao, Kuo-Hsien Cheng, Cheng-Chao Lin, Shao-Ta Hsu, Ying-Lang Wang
  • Patent number: 6732442
    Abstract: An apparatus and method for adjusting the position of a load port utilized in a semiconductor wafer processing system. Generally, a door opener can be configured for opening a door through which a semiconductor wafer may enter for subsequent positioning and processing thereof by a semiconductor wafer processing system. A load port is associated with the door opener. A calibration mechanism can then be utilized for calibrating the load port for leveling and height positioning, such that a plurality of directional axis associated with the load port do not interfere with one another, thereby conserving calibration time while permitting a single individual to perform calibration operations thereof.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: May 11, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yaw-Wen Wu, Tung-Gan Cheng, Tung-Liang Wua, Cheng-Chao Lin, Hsueh-Cheng Lin, Chia-Fu Tsai, Chih-Jung Yeh, Hung-Tse Huang, Ray-Wen Tsai
  • Publication number: 20040006883
    Abstract: An apparatus and method for adjusting the position of a load port utilized in a semiconductor wafer processing system. Generally, a door opener can be configured for opening a door through which a semiconductor wafer may enter for subsequent positioning and processing thereof by a semiconductor wafer processing system. A load port is associated with the door opener. A calibration mechanism can then be utilized for calibrating the load port for leveling and height positioning, such that a plurality of directional axis associated with the load port do not interfere with one another, thereby conserving calibration time while permitting a single individual to perform calibration operations thereof.
    Type: Application
    Filed: July 15, 2002
    Publication date: January 15, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yaw-Wen Wu, Tung-Gan Cheng, Tung-Liang Wua, Cheng-Chao Lin, Hsueh-Cheng Lin, Chia-Fu Tsai, Chih-Jung Yeh, Hung-Tse Huang, Ray-Wen Tsai