Abstract: A method and apparatus for vibro-treating an object. The method includes the steps of controlling a relative displacement between a vibro-treating media and a surface area of the object to provide a vibro-treating effect; and, controlling movement of the object relative to a surface of the vibro-treating media while controlling relative displacement between the vibro-treating media and the surface area of the object, according to one or more pre-determined conditions, to provide a substantially even vibro-treating condition over the surface area of the object.

Abstract: A method and apparatus for vibro-treating an object. The method includes the steps of controlling a relative displacement between a vibro-treating media and a surface area of the object to provide a vibro-treating effect; and, controlling movement of the object relative to a surface of the vibro-treating media whilst controlling relative displacement between the vibro-treating media and the surface area of the object, according to one or more pre-determined conditions, to provide a substantially even vibro-treating condition over the surface area of the object.

Abstract: Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.

Abstract: A semiconductor device has a substrate of one type of semiconductor material, such as silicon. A contact structure is formed on the substrate, and the contact structure is formed of a compound of a metal and a second type of semiconductor material, such as germanium. The contact structure according to embodiments of the present invention include a semiconductor material which a different semiconductor material forming the substrate. Higher or lower barrier height is obtained by embodiment of the invention. A method for forming a contact structure in which a substrate of one type of semiconductor material is provided. A layer of another different semiconductor material is formed on the substrate. A layer of metal is then formed on the layer of the other different semiconductor material. Upon annealing, a contact structure is formed on the substrate, which is a compound of the metal and the other different semiconductor material, onto the substrate.

Abstract: A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.

Abstract: A method for forming a thicker silicide over a MOS device is described. This is achieved using a process where the gate structure is formed by conventional techniques upon a substrate. A low-energy implantation is performed to form lightly doped source and drain (LDD) regions in the substrate in the areas not protected by the gate structure. A first spacer composed of tetraethyl-oxysilane (TEOS oxide), for example, is formed along the sidewalls of the gate structure. A second low-energy implantation is performed to form the source and drain (S/D) in the areas not protected by the gate structure and first spacer. A layer of metal such as titanium (Ti), for example, is then deposited over the surface of the gate structure. A second sidewall spacer composed of titanium nitride (TiN), for example, is formed along the sidewalls of the gate structure covering the metal over the first sidewall spacer and covering the metal over isolation regions.

Abstract: A method for forming a thicker silicide over a MOS device is described. This is achieved using a process where the gate structure is formed by conventional techniques upon a substrate. A low-energy implantation is performed to form lightly doped source and drain (LDD) regions in the substrate in the areas not protected by the gate structure. A first spacer composed of tetraethyl-oxysilane (TEOS oxide), for example, is formed along the sidewalls of the gate structure. A second low-energy implantation is performed to form the source and drain (S/D) in the areas not protected by the gate structure and first spacer. A layer of metal such as titanium (Ti), for example, is then deposited over the surface of the gate structure. A second sidewall spacer composed of titanium nitride (TiN), for example, is formed along the sidewalls of the gate structure covering the metal over the first sidewall spacer. A layer of polysilicon is then deposited over the surface of the gate structure.