Patents by Inventor Cheng-Chen Liu

Cheng-Chen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210168629
    Abstract: Aspects of the subject disclosure include, for example, identifying a primary serving cell and a secondary serving cell, wherein the primary serving cell facilitates one of attachment, re-attachment or mobility, or any combination thereof, of a mobile device in association with coordination of a wireless service between the primary serving cell, the secondary serving cell and the mobile device. A latency value associated with a message exchange is determined between the primary and secondary serving cells via a messaging interface, and compared to latency requirements, which correspond to a group of mobile service features. A mobile service feature of the group is associated with the wireless service based on the comparison. The wireless service includes a coordinated exchange of wireless signals between the primary serving cell and the mobile device and between the secondary serving cell and the mobile device based on the mobile service feature. Other embodiments are disclosed.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Applicants: AT&T Intellectual Property I, L.P., AT&T Mobility II LLC
    Inventors: Hongyan Lei, Ye Chen, Zhi Cui, Cheng P. Liu, Yonghui Tong
  • Publication number: 20210160281
    Abstract: A system for detecting phishing events is provided. A data receiver is configured to receive datasets representative of web traffic associated with access to or on-going usage of an application hosted on a server of a production environment by a user. A machine learning engine is configured to generate a score based at least on the datasets representative of the web traffic indicative of whether the user is a malicious user or a non-malicious user. A routing modification engine is configured to route downstream web traffic associated with access to or on-going usage of the application by the user if the score is greater than a threshold to a server of a sandbox environment that is configured to emulate a graphic user interface of the production environment.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 27, 2021
    Inventors: Matin HALLAJI, Cheng Chen LIU, Ilya KOLMANOVICH, Jamie Robert GAMBLE, Gadi SHIPTS, Cormac O'KEEFFE
  • Publication number: 20210151353
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11004728
    Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yu-Sheng Tang, Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen, Chun-Yen Lo, Kuo-Chio Liu
  • Publication number: 20210126804
    Abstract: A power source device coupled to a power device includes an output port and a controller. When the output port is coupled to a connection cable, the controller is activated to generate a handshake signal, so as to communicate with the power device. When it is determined that the power device is able to be powered according to the handshake signal, the controller controls the power supply device to power the power device through the connection cable. When the connection cable is not coupled to the output port, the controller is deactivated and thus the handshake signal is not generated.
    Type: Application
    Filed: July 13, 2020
    Publication date: April 29, 2021
    Inventors: Yung-Wei PENG, Kuan-Hsien TU, Yen-Lun WU, Cheng-En LIU, Hsuan-Chen LIN
  • Patent number: 8305116
    Abstract: An injection-locked frequency dividing apparatus including a frequency multiplier, a first linear mixer, a second linear mixer, and an oscillator is disclosed. The frequency multiplier receives a frequency signal and generates a multiple-frequency signal accordingly. The first and the second linear mixer both receive the multiple-frequency signal and respectively receive a first input signal and a second input signal, wherein the phases of the first and the second input signal are complementary. The first and the second linear mixer respectively mix the multiple-frequency signal with the first and the second input signal to respectively generate a first mixed signal and a second mixed signal. The oscillator generates the frequency signal. The oscillator further receives the first and the second mixed signal and generates a first output signal and a second output signal accordingly, wherein the phases of the first and the second output signal are complementary.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: November 6, 2012
    Assignee: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Yu-Sheng Chen, Chia-Wei Chang, Cheng-Chen Liu
  • Publication number: 20120062287
    Abstract: An injection-locked frequency dividing apparatus including a frequency multiplier, a first linear mixer, a second linear mixer, and an oscillator is disclosed. The frequency multiplier receives a frequency signal and generates a multiple-frequency signal accordingly. The first and the second linear mixer both receive the multiple-frequency signal and respectively receive a first input signal and a second input signal, wherein the phases of the first and the second input signal are complementary. The first and the second linear mixer respectively mix the multiple-frequency signal with the first and the second input signal to respectively generate a first mixed signal and a second mixed signal. The oscillator generates the frequency signal. The oscillator further receives the first and the second mixed signal and generates a first output signal and a second output signal accordingly, wherein the phases of the first and the second output signal are complementary.
    Type: Application
    Filed: January 26, 2011
    Publication date: March 15, 2012
    Applicant: National Taiwan University of Science and Technoloy
    Inventors: Sheng-Lyang Jang, Yu-Sheng Chen, Chia-Wei Chang, Cheng-Chen Liu
  • Patent number: 8035456
    Abstract: A VCO comprising a cross-coupled transistors module and a resonant module is provided. The resonant module comprises a first transistor, second transistor, a first inductor and varactor string and a second inductor and varactor string. The first source/drain terminal of the first transistor coupled to the second reference voltage, the second source/drain terminal of the first transistor coupled to the cross-coupled transistors module and the gate terminal coupled to a bias voltage. The first source/drain terminal of the second transistor coupled to the second reference voltage, the second source/drain terminal of the second transistor coupled to the cross-coupled transistors module and the gate terminal of the second transistor coupled to the bias voltage. The first and second inductor and varactor strings coupled between the gate of the first and second transistors and a tuning voltage in serial, separately.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: October 11, 2011
    Assignee: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu, Yi-Jhe Song
  • Publication number: 20110241788
    Abstract: A VCO comprising a cross-coupled transistors module and a resonant module is provided. The resonant module comprises a first transistor, second transistor, a first inductor and varactor string and a second inductor and varactor string. The first source/drain terminal of the first transistor coupled to the second reference voltage, the second source/drain terminal of the first transistor coupled to the cross-coupled transistors module and the gate terminal coupled to a bias voltage. The first source/drain terminal of the second transistor coupled to the second reference voltage, the second source/drain terminal of the second transistor coupled to the cross-coupled transistors module and the gate terminal of the second transistor coupled to the bias voltage. The first and second inductor and varactor strings coupled between the gate of the first and second transistors and a tuning voltage in serial, separately.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 6, 2011
    Applicant: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu, Yi-Jhe Song
  • Patent number: 7782101
    Abstract: An injection-locked frequency divider for dividing a frequency of an injection signal and obtaining a frequency divided signal is provided. The injection-locked frequency divider includes a signal injection unit and an oscillator. The signal injection unit includes a first input terminal and a second input terminal for receiving the injection signal. The received injection signal exhibits a phase difference of 180° between the first input terminal and the second input terminal. The oscillator includes an inductor unit and a variable capacitance unit. The injection-locked frequency divider is featured with a wide injection locking range, and can be realized with a low operation voltage, and therefore can be conveniently used in different kinds of hybrid ICs.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 24, 2010
    Assignee: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu
  • Patent number: 7683681
    Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes an active inductor unit, a source injection unit, a first transistor and a second transistor. The injection-locked frequency divider generates a frequency-divided signal having a half frequency of the signal source. A locking frequency range of the injection-locked frequency divider is determined by a quality factor of a resonant cavity. A quality factor of the active inductor unit is lower than a conventional spiral inductor because the active inductor unit is composed of active elements. In the injection-locked frequency divider, the active inductor unit is used to instead of the conventional spiral inductor, so that the chip area can be reduced and the locking frequency range of the injection-locked frequency divider can be increased. Further, an induction value of the active inductor unit can be altered to change the locking frequency range of the injection-locked frequency divider.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 23, 2010
    Assignee: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu, Jui-Cheng Han
  • Patent number: 7659784
    Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes a voltage control oscillator (VCO) and a mixer. The VCO includes a LC resonance tank and a negative-resistance generator for generating a differential oscillation signal including a first and a second oscillation signals. The LC resonance tank adjusts a VCO reactance and resonates for generating the differential oscillation signal. The negative-resistance generator coupled to the LC resonance tank eliminates an equivalent resistance generated by the LC resonance tank and maintains the VCO to continuously oscillate.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: February 9, 2010
    Assignee: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu
  • Publication number: 20090251177
    Abstract: An injection-locked frequency divider for dividing a frequency of an injection signal and obtaining a frequency divided signal is provided. The injection-locked frequency divider includes a signal injection unit and an oscillator. The signal injection unit includes a first input terminal and a second input terminal for receiving the injection signal. The received injection signal exhibits a phase difference of 180° between the first input terminal and the second input terminal. The oscillator includes an inductor unit and a variable capacitance unit. The injection-locked frequency divider is featured with a wide injection locking range, and can be realized with a low operation voltage, and therefore can be conveniently used in different kinds of hybrid ICs.
    Type: Application
    Filed: June 30, 2008
    Publication date: October 8, 2009
    Applicant: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu
  • Publication number: 20090102565
    Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes a voltage control oscillator (VCO) and a mixer. The VCO includes a LC resonance tank and a negative-resistance generator for generating a differential oscillation signal including a first and a second oscillation signals. The LC resonance tank adjusts a VCO reactance and resonates for generating the differential oscillation signal. The negative-resistance generator coupled to the LC resonance tank eliminates an equivalent resistance generated by the LC resonance tank and maintains the VCO to continuously oscillate.
    Type: Application
    Filed: December 28, 2007
    Publication date: April 23, 2009
    Applicant: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu
  • Publication number: 20080278204
    Abstract: An injection-locked frequency divider is provided. The present invention includes an active inductor unit, a source injection unit, a first transistor and a second transistor. A first terminal of the active inductor unit is coupled to a first voltage. A first terminal of the source injection unit receives a signal source. A second terminal and a third terminal of the source injection unit are respectively coupled to a second terminal and a third terminal of the active inductor unit. A first terminal, a gate terminal and a second terminal of the first transistor are respectively coupled to the second terminal and the third terminal of the source injection unit and a second voltage. A first terminal, a gate terminal and a second terminal of the second transistor are respectively coupled to the third terminal and a second terminal of the source injection unit and the second voltage.
    Type: Application
    Filed: December 12, 2007
    Publication date: November 13, 2008
    Applicant: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu, Jui-Cheng Han