Abstract: A recycling apparatus for a solar cell module includes a platform for supporting and positioning the solar cell module, and at least one milling device disposed on the platform and having a milling member configured to contact a back plate of the solar cell module, and a casing defining a chip-receiving space and having an air inlet and a suction port communicating with the chip-receiving space. A drive device is connected to the at least one milling device for driving the at least one milling device to move around and mill the solar cell module through the milling member.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: Disclosed are an in-memory computing architecture for a nearest neighbor search of a cosine distance and an operating method thereof. The in-memory computing architecture comprises two FeFET-based storage arrays, Translinear circuits and a WTA circuit, and the two storage arrays are a first storage array and a second storage array, respectively; wherein each of the storage cells comprises a FeFET and a resistor which are electrically connected; an input vector is inputted into the first storage array for outputting the inner product X of the input vector multiplied by all the storage vectors in the first storage array; the second storage array outputs the sum of squares Y of all vector elements in the storage vectors; the output values of the first storage array and the second storage array are respectively inputted into the Translinear circuits through current mirrors; and the Translinear circuits output X2/Y to the WTA circuit.

Abstract: A system for detecting phishing events is provided. A data receiver is configured to receive datasets representative of web traffic associated with access to or on-going usage of an application hosted on a server of a production environment by a user. A machine learning engine is configured to generate a score based at least on the datasets representative of the web traffic indicative of whether the user is a malicious user or a non-malicious user. A routing modification engine is configured to route downstream web traffic associated with access to or on-going usage of the application by the user if the score is greater than a threshold to a server of a sandbox environment that is configured to emulate a graphic user interface of the production environment.

Abstract: A system for detecting phishing events is provided. A data receiver is configured to receive datasets representative of web traffic associated with access to or on-going usage of an application hosted on a server of a production environment by a user. A machine learning engine is configured to generate a score based at least on the datasets representative of the web traffic indicative of whether the user is a malicious user or a non-malicious user. A routing modification engine is configured to route downstream web traffic associated with access to or on-going usage of the application by the user if the score is greater than a threshold to a server of a sandbox environment that is configured to emulate a graphic user interface of the production environment.

Abstract: A computer system for, and method of, detecting fraudulent electronic transactions is provided. The system comprises at least one processor and a memory storing instructions which when executed by the processor configure the processor to perform the method. The method comprises accessing a trained model, receiving real-time transaction data, extracting graph-based and statistical features to enrich the real-time transaction data, and determining an account proximity score for the real-time transaction data.

Abstract: A system for detecting phishing events is provided. A data receiver is configured to receive datasets representative of web traffic associated with access to or on-going usage of an application hosted on a server of a production environment by a user. A machine learning engine is configured to generate a score based at least on the datasets representative of the web traffic indicative of whether the user is a malicious user or a non-malicious user. A routing modification engine is configured to route downstream web traffic associated with access to or on-going usage of the application by the user if the score is greater than a threshold to a server of a sandbox environment that is configured to emulate a graphic user interface of the production environment.

Abstract: An injection-locked frequency dividing apparatus including a frequency multiplier, a first linear mixer, a second linear mixer, and an oscillator is disclosed. The frequency multiplier receives a frequency signal and generates a multiple-frequency signal accordingly. The first and the second linear mixer both receive the multiple-frequency signal and respectively receive a first input signal and a second input signal, wherein the phases of the first and the second input signal are complementary. The first and the second linear mixer respectively mix the multiple-frequency signal with the first and the second input signal to respectively generate a first mixed signal and a second mixed signal. The oscillator generates the frequency signal. The oscillator further receives the first and the second mixed signal and generates a first output signal and a second output signal accordingly, wherein the phases of the first and the second output signal are complementary.

Abstract: An injection-locked frequency dividing apparatus including a frequency multiplier, a first linear mixer, a second linear mixer, and an oscillator is disclosed. The frequency multiplier receives a frequency signal and generates a multiple-frequency signal accordingly. The first and the second linear mixer both receive the multiple-frequency signal and respectively receive a first input signal and a second input signal, wherein the phases of the first and the second input signal are complementary. The first and the second linear mixer respectively mix the multiple-frequency signal with the first and the second input signal to respectively generate a first mixed signal and a second mixed signal. The oscillator generates the frequency signal. The oscillator further receives the first and the second mixed signal and generates a first output signal and a second output signal accordingly, wherein the phases of the first and the second output signal are complementary.

Abstract: A VCO comprising a cross-coupled transistors module and a resonant module is provided. The resonant module comprises a first transistor, second transistor, a first inductor and varactor string and a second inductor and varactor string. The first source/drain terminal of the first transistor coupled to the second reference voltage, the second source/drain terminal of the first transistor coupled to the cross-coupled transistors module and the gate terminal coupled to a bias voltage. The first source/drain terminal of the second transistor coupled to the second reference voltage, the second source/drain terminal of the second transistor coupled to the cross-coupled transistors module and the gate terminal of the second transistor coupled to the bias voltage. The first and second inductor and varactor strings coupled between the gate of the first and second transistors and a tuning voltage in serial, separately.

Abstract: A VCO comprising a cross-coupled transistors module and a resonant module is provided. The resonant module comprises a first transistor, second transistor, a first inductor and varactor string and a second inductor and varactor string. The first source/drain terminal of the first transistor coupled to the second reference voltage, the second source/drain terminal of the first transistor coupled to the cross-coupled transistors module and the gate terminal coupled to a bias voltage. The first source/drain terminal of the second transistor coupled to the second reference voltage, the second source/drain terminal of the second transistor coupled to the cross-coupled transistors module and the gate terminal of the second transistor coupled to the bias voltage. The first and second inductor and varactor strings coupled between the gate of the first and second transistors and a tuning voltage in serial, separately.

Abstract: An injection-locked frequency divider for dividing a frequency of an injection signal and obtaining a frequency divided signal is provided. The injection-locked frequency divider includes a signal injection unit and an oscillator. The signal injection unit includes a first input terminal and a second input terminal for receiving the injection signal. The received injection signal exhibits a phase difference of 180° between the first input terminal and the second input terminal. The oscillator includes an inductor unit and a variable capacitance unit. The injection-locked frequency divider is featured with a wide injection locking range, and can be realized with a low operation voltage, and therefore can be conveniently used in different kinds of hybrid ICs.

Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes an active inductor unit, a source injection unit, a first transistor and a second transistor. The injection-locked frequency divider generates a frequency-divided signal having a half frequency of the signal source. A locking frequency range of the injection-locked frequency divider is determined by a quality factor of a resonant cavity. A quality factor of the active inductor unit is lower than a conventional spiral inductor because the active inductor unit is composed of active elements. In the injection-locked frequency divider, the active inductor unit is used to instead of the conventional spiral inductor, so that the chip area can be reduced and the locking frequency range of the injection-locked frequency divider can be increased. Further, an induction value of the active inductor unit can be altered to change the locking frequency range of the injection-locked frequency divider.

Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes a voltage control oscillator (VCO) and a mixer. The VCO includes a LC resonance tank and a negative-resistance generator for generating a differential oscillation signal including a first and a second oscillation signals. The LC resonance tank adjusts a VCO reactance and resonates for generating the differential oscillation signal. The negative-resistance generator coupled to the LC resonance tank eliminates an equivalent resistance generated by the LC resonance tank and maintains the VCO to continuously oscillate.

Abstract: An injection-locked frequency divider for dividing a frequency of an injection signal and obtaining a frequency divided signal is provided. The injection-locked frequency divider includes a signal injection unit and an oscillator. The signal injection unit includes a first input terminal and a second input terminal for receiving the injection signal. The received injection signal exhibits a phase difference of 180° between the first input terminal and the second input terminal. The oscillator includes an inductor unit and a variable capacitance unit. The injection-locked frequency divider is featured with a wide injection locking range, and can be realized with a low operation voltage, and therefore can be conveniently used in different kinds of hybrid ICs.

Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes a voltage control oscillator (VCO) and a mixer. The VCO includes a LC resonance tank and a negative-resistance generator for generating a differential oscillation signal including a first and a second oscillation signals. The LC resonance tank adjusts a VCO reactance and resonates for generating the differential oscillation signal. The negative-resistance generator coupled to the LC resonance tank eliminates an equivalent resistance generated by the LC resonance tank and maintains the VCO to continuously oscillate.

Abstract: An injection-locked frequency divider is provided. The present invention includes an active inductor unit, a source injection unit, a first transistor and a second transistor. A first terminal of the active inductor unit is coupled to a first voltage. A first terminal of the source injection unit receives a signal source. A second terminal and a third terminal of the source injection unit are respectively coupled to a second terminal and a third terminal of the active inductor unit. A first terminal, a gate terminal and a second terminal of the first transistor are respectively coupled to the second terminal and the third terminal of the source injection unit and a second voltage. A first terminal, a gate terminal and a second terminal of the second transistor are respectively coupled to the third terminal and a second terminal of the source injection unit and the second voltage.