Patents by Inventor Cheng-Cheng Guo

Cheng-Cheng Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Damascene method employing multi-layer etch stop layer
    Patent number: 6734116
    Abstract: Within a damascene method for forming a microelectronic fabrication, there is employed an etch stop layer comprising a comparatively low dielectric constant dielectric material sub-layer having formed thereupon a comparatively high dielectric constant dielectric material sub-layer. Within the method there is also simultaneously etched: (1) an anti-reflective coating layer from an inter-metal dielectric layer; and (2) the etch stop layer from a contact region. The microelectronic fabrication is formed with enhanced performance and enhanced reliability.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: May 11, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Cheng Guo, Dian-Hau Chen, Li-Kong Turn, Han-Ming Sheng
  • Damascene method employing multi-layer etch stop layer
    Publication number: 20030134521
    Abstract: Within a damascene method for forming a microelectronic fabrication, there is employed an etch stop layer comprising a comparatively low dielectric constant dielectric material sub-layer having formed thereupon a comparatively high dielectric constant dielectric material sub-layer. Within the method there is also simultaneously etched: (1) an anti-reflective coating layer from an inter-metal dielectric layer; and (2) the etch stop layer from a contact region. The microelectronic fabrication is formed with enhanced performance and enhanced reliability.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Cheng Guo, Dian-Hau Chen, Li-Kong Turn, Han-Ming Sheng