Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: An object detection device and a confidence threshold method adjustment method are provided. The object detection device includes an optical camera, multiple sensors, and a processor. The optical camera and sensors are used to respectively capture a real-time video and environmental value of a detection area. The processor performs an object recognition model and at least one second recognition model. The object recognition model determines whether an object exists in the detection area based on the real-time video to generate a first recognition result and a corresponding first confidence value. The at least one second recognition model generates a second result based on the environmental value respectively. The processor dynamically adjusts a confidence threshold value based on a value of the second result and a correlation degree between the object and the second result.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures, and the semiconductor nanostructures are adjacent to an epitaxial structure. The method also includes forming a dielectric layer over the metal gate stack and the epitaxial structure and partially removing the dielectric layer to form a contact opening exposing the epitaxial structure. The method further includes forming a first protective layer over sidewalls of the contact opening and forming a second protective layer over the first protective layer. The first protective layer has a lower dielectric constant than that of the second protective layer. In addition, the method includes forming a conductive contact over the second protective layer and the epitaxial structure to fill the contact opening.

Abstract: A method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

Abstract: An electronic device includes an electronic unit and a circuit structure. The circuit structure is electrically connected to the electronic unit and includes a first circuit structure, a second circuit structure, a bonding pad, and an adjustment layer. The first circuit structure includes at least one first circuit layer and at least one first insulation layer. The second circuit structure is disposed between the electronic unit and the first circuit structure, and includes at least one second circuit layer and at least one second insulation layer. The bonding pad and the adjustment layer are disposed between the second circuit structure and the first circuit structure. A coefficient of thermal expansion of the adjustment layer is smaller than that of at least one of the at least one first insulation layer of the first circuit structure and the at least one second insulation layer of the second circuit structure.

Abstract: An electronic device including a circuit layer, an electronic element, a first flow-path structure and a fluid material is disclosed. The electronic element is disposed on the circuit layer and electrically connected to the circuit layer. The first flow-path structure includes a first flow path, and the electronic element is disposed in the first flow-path structure. The fluid material is disposed in the first flow path. The fluid material is used for performing heat exchange with the electronic element. The circuit layer includes an input hole and an output hole, and the fluid material enters the first flow path through the input hole and exits the first flow path through the output hole.

Abstract: A method of forming a part includes 3D printing a photopolymerizable resin and forming a preformed part and subsequently post-curing the preformed part with electron beams. The preformed part may be cured via UV curing. A section of the preformed part post-cured with electron beams may have a thickness of at least 1.0 centimeter, for example, at least 2.0 centimeters or at least 3.0 centimeters. An electron beam dosage to post-cure the preformed part may be between 10 kilogray (kGy) and 100 kGy. The preformed part may be 3D printed using stereolithography (SLA), digital light processing (DLP) or material jetting (MJ) and the photopolymerizable resin may include at least one of an acrylate functional polymer and a methacrylate functional polymer. In the alternative, or in addition to, the photopolymerizable resin may include at least one of a urethane, a polyester, and a polyether.

Abstract: A memory device and formation thereof. The memory device includes a stack of memory dies. Each memory die in the stack of memory dies includes two or more layers of memory devices.

Abstract: An integrated circuit includes a strip structure having a front side and a back side. The integrated circuit includes a gate structure on the front side of the strip structure. The integrated circuit includes an isolation structure surrounding the strip structure. The integrated circuit includes a backside via in the isolation structure. The integrated circuit includes a contact over the strip structure, wherein a first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and in contact with the backside via.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Abstract: Provided herein are compounds, pharmaceutical compositions, and methods of treatment for various diseases or conditions, such as cancer. In one aspect, the method comprises the treatment of metastatic cancers. Compounds and methods provided herein are also used for the treatment of diseases such as inflammatory disease, cardiovascular disease, autoimmune disease, and dry eye syndrome. Further provided herein are dietary supplement formulations and methods for supporting a healthy lifestyle.

Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.