Patents by Inventor Cheng Chi

Cheng Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651183
    Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 12, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Jianjun Yang, Cheng-Hua Yang, Fan-Chi Meng, Chih-Chien Chang, Shen-De Wang
  • Publication number: 20200143099
    Abstract: A method includes obtaining a layout of a circuit pattern implemented on a semiconductor wafer, and identifying one or more polygons in the layout based on a length criteria. One or more measurement gauges are placed on the identified polygons to thereby obtain measured polygons. A scanning electron microscope (SEM) image of the circuit pattern is obtained. The SEM image is aligned with the layout including the measured polygons. A critical dimension of one or more objects in the SEM image is measured. The one or more objects correspond to the one or more polygons. Based on the measured critical dimension, it is determined whether the circuit pattern is acceptable.
    Type: Application
    Filed: August 15, 2019
    Publication date: May 7, 2020
    Inventors: Cheng-Chi WU, Wen-Chuan WANG
  • Publication number: 20200134480
    Abstract: An apparatus and method for detecting impact factors for an operating environment. The apparatus generates a detection result for each of the first factors of a plurality of first historical records by analyzing a dissimilarity degree of the plurality of first data corresponding to each first factor. Each detection result is a continuous data type or a discrete data type. The apparatus trains a data type recognition model according to the first historical records and the detection results. The apparatus establishes a basic prediction model by a training set of a plurality of second historical records, generates a comparison set by rearranging the second data corresponding to a specific factor in the training set, establishes a comparison prediction model by the comparison set, and determines a degree of importance of the specific factor by comparing the accuracies of the basic prediction model and the comparison prediction model.
    Type: Application
    Filed: November 29, 2018
    Publication date: April 30, 2020
    Inventors: Huan-Chi PENG, Yu-Xuan SU, Yin-Jing TIEN, Yi-Hsin WU, Cheng-Juei YU
  • Publication number: 20200133118
    Abstract: A method for manufacturing a photomask is provided. The method includes: receiving a substrate having a hard mask disposed thereover; forming a patterned photoresist over the hard mask; patterning the hard mask using the patterned photoresist as a mask; and removing the patterned photoresist. The removing of the patterned photoresist includes: oxidizing organic materials over the substrate; applying an alkaline solution onto the patterned photoresist; and removing the patterned photoresist by mechanical impact. A method for cleaning a substrate and a photomask are also provided.
    Type: Application
    Filed: February 14, 2019
    Publication date: April 30, 2020
    Inventors: YU-HSIN HSU, HAO-MING CHANG, SHAO-CHI WEI, SHENG-CHANG HSU, CHENG-MING LIN
  • Publication number: 20200135857
    Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 30, 2020
    Inventors: Yun-Chi WU, Tsung-Yu YANG, Cheng-Bo SHU, Chien Hung LIU
  • Publication number: 20200121982
    Abstract: An elliptical machine includes a base and an upright column fixed to the base; a transmission mechanism mounted on the base, the bases on both sides of which are respectively provided with the link mechanism connected with the transmission mechanism wherein each link mechanism includes a first link rod connected with the transmission mechanism, and a second link rod having a pedal and connected with the first link rod. The first link rod is telescopic and connected to the base. When the user uses the pedal of two link mechanisms to link the transmission mechanism through the link rods, the total length of the first link rod is reciprocatingly and continuously changed, so that the top end of the first link rod can make the circulatory movement along an elliptical path, and interlocks the second link rod, and the pedal synchronously can make the circulatory movement along an elliptical path.
    Type: Application
    Filed: April 4, 2019
    Publication date: April 23, 2020
    Inventors: Chao-Chi YU, Cheng-Ru YU
  • Publication number: 20200126774
    Abstract: A method and apparatus for dosage measurement and monitoring in an ion implantation system is disclosed. In one embodiment, a transferring system, includes: a vacuum chamber, wherein the vacuum chamber is coupled to a processing chamber; a shaft coupled to a ball screw, wherein the ball screw and the shaft are configured in the vacuum chamber; and a vacuum rotary feedthrough, wherein the vacuum rotary feedthrough comprises a magnetic fluid seal so as to provide a high vacuum sealing, and wherein the vacuum rotary feedthrough is configured through a first end of the vacuum chamber and coupled to the ball screw so as to provide a rotary motion on the ball screw.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 23, 2020
    Inventors: Tsung-Min LIN, Fang-Chi Chien, Cheng-Yi Huang, Chao-Po Lu
  • Publication number: 20200126976
    Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Yu CHEN, Chih-Ping CHAO, Chun-Hung CHEN, Chung-Long CHANG, Kuan-Chi TSAI, Wei-Kung TSAI, Hsiang-Chi CHEN, Ching-Chung HSU, Cheng-Chang HSU, Yi-Sin WANG
  • Patent number: 10629568
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Publication number: 20200117032
    Abstract: A display device includes a first panel and a second panel disposed on the first panel. The first panel has a first working area and a plurality of pixel areas disposed in the first working area. The second panel has a second working area and a plurality of pixel areas disposed in the second working area. The second working area overlaps with the first working area, and the second working area is smaller than the first working area.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 16, 2020
    Inventors: Chien-Hung CHAN, Jin-Yi TAN, Cheng-Tso HSIAO, Huang-Chi CHAO, Ming-Feng HSIEH, Ying-Jen CHEN
  • Publication number: 20200119019
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10622475
    Abstract: Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Bentley, Cheng Chi, Chanro Park, Ruilong Xie, Tenko Yamashita
  • Publication number: 20200110275
    Abstract: An imaging lens assembly includes a plastic barrel and an imaging lens set. The plastic barrel includes an object-side aperture and a first annular surface. The imaging lens set includes a plurality of optical elements, wherein at least one of the optical elements is a plastic lens element, and the plastic lens element includes an effective optical portion, a peripheral portion, a second annular surface, and an object-side connecting surface. The peripheral portion is formed around the effective optical portion. The second annular surface is formed on an object-side surface of the plastic lens element and surrounds the effective optical portion. The object-side connecting surface is formed on the object-side surface of the plastic lens element and surrounds the effective optical portion, and the object-side connecting surface is connected with one of the optical elements disposed on an object side of the plastic lens element.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 9, 2020
    Inventors: Hsiang-Chi TANG, Cheng-Chen LIN, Ming-Ta CHOU
  • Publication number: 20200111702
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Patent number: 10615416
    Abstract: A negative electrode material applied to a lithium battery or a sodium battery is provided. The negative electrode material is composed of a first chemical element, a second chemical element and a third chemical element with an atomic ratio of x, 1?x, and 2, wherein 0<x<1, the first chemical element is selected from the group consisting of molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn), technetium (Tc) and rhenium (Re), the second chemical element is selected from the group consisting of Mo, Cr and W, the third chemical element is selected from the group consisting of sulfur (S), selenium (Se) and tellurium (Te), and the first chemical element is different from the second chemical element.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 7, 2020
    Assignee: Chung-Yuan Christian University
    Inventors: Chun-Chuen Yang, Wei-Jen Liu, Yung-Hsiang Tung, Irish Valerie Buiser Maggay, Cheng-Wei Kao, Tung-Chi Tsai
  • Patent number: 10615525
    Abstract: An electronic device is provided. The electronic device includes a substrate, a connector, a ground bracket and a conductive structure. The substrate includes a ground layer. The connector is disposed on the substrate, wherein the connector includes a metal frame. The ground bracket is affixed on the substrate and coupled to the ground layer, wherein at least a portion of the connector is located in the ground bracket. The conductive structure is adapted to abut the metal frame and to abut the ground bracket, wherein when the conductive structure connects the metal frame to the ground bracket, the conductive structure electrically connects the ground bracket to the metal frame.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 7, 2020
    Assignee: WISTRON NEWEB CORP.
    Inventors: Yi-Chieh Lin, San-Yi Kuo, Man-Ning Lu, Cheng-Hsiung Lu, Huei-Chi Wu, Yu-Cheng Yu
  • Publication number: 20200105660
    Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.
    Type: Application
    Filed: August 28, 2019
    Publication date: April 2, 2020
    Inventors: Kam-Tou SIO, Cheng-Chi CHUANG, Chih-Ming LAI, Jiann-Tyng TZENG, Wei-Cheng LIN, Lipen YUAN
  • Patent number: 10607662
    Abstract: A Static Random Access Memory (SRAM) array power supply circuit is presented. The circuit comprises an SRAM test unit having a substantially same structure as a basic SRAM unit in the SRAM array; a switch device connected to a power source, the SRAM test unit, and the SRAM array; and a switch control circuit connected to the SRAM test unit and the switch device. When a test voltage in the SRAM test unit is lower than a threshold voltage, the switch device is closed so that the power source begins to charge the SRAM array and the SRAM test unit. The SRAM test unit provides an early warning for the SRAM array, allowing the latter to be charged upon fulfillment of a condition (e.g., charge is low). Compared to conventional circuits, this circuit provides an output voltage that is more stable and less susceptible to the changes in external conditions such as temperature or pressure.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 31, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chen-Yi Huang, Chia Chi Yang, Dong Xiang Luo, Cheng-Tai Huang
  • Patent number: 10602110
    Abstract: Methods and systems for chroma reshaping are applied to images or video frames. The method comprises receiving at least one image or video frame. The color space of the at least one image or video frame is partitioned in M1×M2×M3 non-overlapping bins. For each bin it is determined whether it is a valid bin, for which the at least one image or video frame has at least one pixel with a color value falling within said bin. For each chroma channel, a required number of codewords is calculated for representing two color values in said valid bin that have consecutive codewords for the respective chroma channel without a noticeable difference. At least one content-aware chroma forward reshaping function is generated based on the calculated required numbers of codewords and applied to the at least one image or video frame.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 24, 2020
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Cheng-Chi Li, Guan-Ming Su
  • Patent number: 10594121
    Abstract: Enclosure assemblies with integrating flashing for protecting an accessory on a rooftop. The enclosure assemblies can include a base configured to protect the rooftop from water intrusion and a cover configured to be joined to the raised portion of the base. The base can include a bottom wall and a raised portion extending from the bottom wall. The base can include an uphill portion configured to be positioned beneath at least one full course of roof shingle on the rooftop, without having to cut the roof shingle. The raised portion can be disposed off-center relative to the central transverse axis of the bottom wall, leaving the uphill portion of the bottom wall uncovered.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 17, 2020
    Assignee: Vynckier Enclosure Systems, Inc.
    Inventors: Alex Cheng-Chi Yang, Byron James Madden, Ryan Mac McClister