Patents by Inventor Cheng-Chi Hsieh

Cheng-Chi Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240102860
    Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Cheng Chih HSIEH, Tien Chi WU, Ming-Long LEE, Yu-Hsuan LIN, Tsung-I LIN, Chien-Hao MA
  • Publication number: 20240098016
    Abstract: A method for performing adaptive multi-link aggregation dispatching control in multi-link operation architecture and associated apparatus are provided.
    Type: Application
    Filed: June 19, 2023
    Publication date: March 21, 2024
    Applicant: MEDIATEK INC.
    Inventors: Kuo-Wei Chen, Chia-Shun Wan, Cheng-En Hsieh, Po-Chi Chen
  • Patent number: 8775771
    Abstract: A block management method for managing a plurality of physical blocks of a flash memory chip is provided. The block management method includes configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks; and mapping the logical blocks to the physical blocks. Additionally, the block management method also includes obtaining deleting records related to a plurality of deleted logical addresses from a host system, wherein data stored in the deleted logical addresses is recognized as invalid by the host system. And, the block management method further includes obtaining a deleted logical block, marking each of the logical addresses mapped to the deleted logical block as a bad logical address, and linking the physical block mapped to the deleted logical block to a spare area. Accordingly, the block management method can effectively prolong the lifespan of a flash memory chip.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: July 8, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Kang Yeh, Cheng-Chi Hsieh
  • Patent number: 8037233
    Abstract: A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: October 11, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Khein-Seng Pua, Chung-Hsun Ma, Ming-Jen Liang, Cheng-Chi Hsieh, Chih-Ling Wang
  • Publication number: 20110078363
    Abstract: A block management method for managing a plurality of physical blocks of a flash memory chip is provided. The block management method includes configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks; and mapping the logical blocks to the physical blocks. Additionally, the block management method also includes obtaining deleting records related to a plurality of deleted logical addresses from a host system, wherein data stored in the deleted logical addresses is recognized as invalid by the host system. And, the block management method further includes obtaining a deleted logical block, marking each of the logical addresses mapped to the deleted logical block as a bad logical address, and linking the physical block mapped to the deleted logical block to a spare area. Accordingly, the block management method can effectively prolong the lifespan of a flash memory chip.
    Type: Application
    Filed: October 26, 2009
    Publication date: March 31, 2011
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Cheng-Chi Hsieh
  • Publication number: 20090198877
    Abstract: A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified.
    Type: Application
    Filed: July 18, 2008
    Publication date: August 6, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Khein-Seng Pua, Chung-Hsun Ma, Ming-Jen Liang, Cheng-Chi Hsieh, Chih-Ling Wang
  • Patent number: 6648729
    Abstract: A controlled pressure regulation system generates the wafer-pressing pressures during a polishing operation. A wafer carrier head holds a wafer to be polished against a platen. A first and second pressure regulators respectively generate a first and second pressure onto the platen and the wafer carrier head to press the wafer to be polished. A first and second controllers are respectively connected to the first and second pressure regulators in control feedback loops to control the generation of the first and second pressures. The first and second pressures are controlled to obtain a desired difference of pressure between the first and second pressure.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: November 18, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Hsin Lai, Cheng-Chi Hsieh, Jung-Nan Tseng, Huang-Yi Lin, Fu-Yang Yu
  • Publication number: 20030022595
    Abstract: A controlled pressure regulation system generates the wafer-pressing pressures during a polishing operation. A wafer carrier head holds a wafer to be polished against a platen. A first and second pressure regulators respectively generate a first and second pressure onto the platen and the wafer carrier head to press the wafer to be polished. A first and second controllers are respectively connected to the first and second pressure regulators in control feedback loops to control the generation of the first and second pressures. The first and second pressures are controlled to obtain a desired difference of pressure between the first and second pressure.
    Type: Application
    Filed: June 14, 2002
    Publication date: January 30, 2003
    Inventors: Chien-Hsin Lai, Cheng-Chi Hsieh, Jung-Nan Tseng, Huang-Yi Lin, Fu-Yang Yu