Patents by Inventor Cheng-Chi Huang

Cheng-Chi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10815456
    Abstract: The present disclosure provides for a cryopreservation composition comprising a permeating cryoprotectant, a saccharide and a macromolecule. The cryopreservation composition has a low toxicity to cells and tissues, and promotes survival and retention of viability of the biological material during cryopreservation.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: October 27, 2020
    Assignee: TRANSWELL BIOTECH CO., LTD.
    Inventors: Bin-Ru She, Kun-Chi Chiang, Cheng-Yi Lin, Ting-Yu Huang
  • Patent number: 10811377
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Publication number: 20200321476
    Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Cheng-Bo SHU, Yun-Chi WU, Chung-Jen HUANG
  • Publication number: 20200321294
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu WEI, Cheng-Yuan LI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Publication number: 20200312930
    Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk in a display, the pixel definition layer may disrupt continuity of the OLED layers. The pixel definition layer may have an undercut to disrupt continuity of some but not all of the OLED layers. The undercut may be defined by three discrete portions of the pixel definition layer. The undercut may result in a void that is interposed between different portions of the OLED layers to break a leakage path formed by the OLED layers.
    Type: Application
    Filed: January 16, 2020
    Publication date: October 1, 2020
    Inventors: Jaein Choi, Hairong Tang, Gloria Wong, Sunggu Kang, Younggu Lee, Gwanwoo Park, Chun-Yao Huang, Andrew Lin, Cheuk Chi Lo, Enkhamgalan Dorjgotov, Michael Slootsky, Rui Liu, Wendi Chang, Cheng Chen
  • Patent number: 10790414
    Abstract: A light emitting diode includes an N-type semiconductor layer, a P-type semiconductor layer, and a light emitting layer. The P-type semiconductor layer is located on the N-type semiconductor layer. The light emitting layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The N-type semiconductor layer has a first region and a second region connected to each other. The first region is overlapped with the light emitting layer and the P-type semiconductor layer in a first direction. The second region is not overlapped with the light emitting layer and the P-type semiconductor layer in the first direction. A sheet resistance of the P-type semiconductor layer is smaller than a sheet resistance of the N-type semiconductor layer.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 29, 2020
    Assignee: Au Optronics Corporation
    Inventors: Pu-Jung Huang, Pin-Miao Liu, Cheng-Yeh Tsai, Chen-Chi Lin
  • Publication number: 20200251214
    Abstract: A liver fibrosis assessment model includes following establishing steps. A reference database is obtained, wherein the reference database includes a plurality of reference blood test data. A preprocessing step of the blood test data is performed. A feature extracting step is performed, wherein the feature extracting step is for extracting at least one eigenvalue according to the reference database. A normalizing step of the blood test data is performed. A classifying step is performed, wherein the classifying step is for achieving a convergence of the normalized reference blood test data by using a gradient boosting algorithm so as to obtain the liver fibrosis assessment model. The liver fibrosis assessment model is used to assess whether a subject suffers from liver fibrosis and predict a degree of liver fibrosis of the subject.
    Type: Application
    Filed: December 3, 2019
    Publication date: August 6, 2020
    Applicant: China Medical University Hospital
    Inventors: Tzung-Chi Huang, Ken Ying-Kai Liao, Cheng-Yuan Peng
  • Publication number: 20200230149
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 23, 2020
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao
  • Publication number: 20200230105
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 23, 2020
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao
  • Patent number: 10692826
    Abstract: A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 10693018
    Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Bo Shu, Yun-Chi Wu, Chung-Jen Huang
  • Patent number: 10661408
    Abstract: A stopper includes a head portion sized and configured to be coupled to an upper platen of a chemical-mechanical planarization system and a stopper leg sized and configured to direct a flow of liquid slurry applied to an upper planar surface of the upper platen substantially away from a lower surface of the upper platen.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Han, Cheng-Yi Huang, Fang-Chi Chien, Chen-shih Chung, Sheng-Tai Peng
  • Publication number: 20200126774
    Abstract: A method and apparatus for dosage measurement and monitoring in an ion implantation system is disclosed. In one embodiment, a transferring system, includes: a vacuum chamber, wherein the vacuum chamber is coupled to a processing chamber; a shaft coupled to a ball screw, wherein the ball screw and the shaft are configured in the vacuum chamber; and a vacuum rotary feedthrough, wherein the vacuum rotary feedthrough comprises a magnetic fluid seal so as to provide a high vacuum sealing, and wherein the vacuum rotary feedthrough is configured through a first end of the vacuum chamber and coupled to the ball screw so as to provide a rotary motion on the ball screw.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 23, 2020
    Inventors: Tsung-Min LIN, Fang-Chi Chien, Cheng-Yi Huang, Chao-Po Lu
  • Publication number: 20200119019
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10607662
    Abstract: A Static Random Access Memory (SRAM) array power supply circuit is presented. The circuit comprises an SRAM test unit having a substantially same structure as a basic SRAM unit in the SRAM array; a switch device connected to a power source, the SRAM test unit, and the SRAM array; and a switch control circuit connected to the SRAM test unit and the switch device. When a test voltage in the SRAM test unit is lower than a threshold voltage, the switch device is closed so that the power source begins to charge the SRAM array and the SRAM test unit. The SRAM test unit provides an early warning for the SRAM array, allowing the latter to be charged upon fulfillment of a condition (e.g., charge is low). Compared to conventional circuits, this circuit provides an output voltage that is more stable and less susceptible to the changes in external conditions such as temperature or pressure.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 31, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Chen-Yi Huang, Chia Chi Yang, Dong Xiang Luo, Cheng-Tai Huang
  • Publication number: 20200081286
    Abstract: A sensing display apparatus includes a pixel array substrate, a sensing device substrate, and a display medium layer. The sensing device substrate includes a first substrate, a sensing device, first to third signal lines, and a shielding layer. The sensing device includes a first switching element electrically connected with the first and second signal lines, an electrically conductive layer electrically connected with the third signal line, an electrode layer electrically connected with the first switching element and a photo-sensitive layer disposed between the electrically conductive layer and the electrode layer. The shielding layer is disposed between the first to third signal lines and the pixel array substrate. The sensing display apparatus has light transmitting regions and a light shielding region surrounding the light transmitting regions. The sensing device and the first to third signal lines are disposed in the light shielding region.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 12, 2020
    Applicant: Au Optronics Corporation
    Inventors: Shu-Wen Tzeng, Yen-Hua Lo, Chia-Chi Lee, Cheng-Hsiang Huang
  • Publication number: 20200066815
    Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk in a display, the pixel definition layer may disrupt continuity of the OLED layers. The pixel definition layer may have a steep sidewall, a sidewall with an undercut, or a sidewall surface with a plurality of curves to disrupt continuity of the OLED layers. A control gate that is coupled to a bias voltage and covered by gate dielectric may be used to form an organic thin-film transistor that shuts the leakage current channel between adjacent anodes on the display.
    Type: Application
    Filed: April 27, 2018
    Publication date: February 27, 2020
    Inventors: Jaein Choi, Andrew Lin, Cheuk Chi Lo, Chun-Yao Huang, Gloria Wong, Hairong Tang, Hitoshi Yamamoto, James E. Pedder, KiBeom Kim, Kwang Ohk Cheon, Lei Yuan, Michael Slootsky, Rui Liu, Steven E. Molesa, Sunggu Kang, Wendi Chang, Chun-Ming Tang, Cheng Chen, Ivan Knez, Enkhamgalan Dorjgotov, Giovanni Carbone, Graham B. Myhre, Jungmin Lee
  • Publication number: 20200035695
    Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 30, 2020
    Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
  • Patent number: 10527667
    Abstract: Method and device for detecting the process corner of a transistor are provided. The process corner detection method includes providing a ring oscillator. The ring oscillator includes an odd number of oscillation units connected in series and an output port of one of the oscillation units serves as the output port of the ring oscillator to output an oscillation signal. Each oscillation unit is constructed based on a PMOS transistor and an NMOS transistor. The process corner detection method further includes measuring the period of the oscillation signal and the maintaining time of the oscillation signal at a high level and a low level in each cycle; and determining the process corner of the PMOS transistor and the NMOS transistor in the oscillation unit based on the period of the oscillation signal and the maintaining time of the oscillation signal at a high level and a low level in each cycle.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 7, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Cheng-Tai Huang, Chia Chi Yang, Chen-Yi Huang
  • Publication number: 20200006365
    Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu