Abstract: A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.

Abstract: A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.

Abstract: A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.

Abstract: A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.

Abstract: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.

Abstract: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.