Patents by Inventor Cheng-Chi Liu
Cheng-Chi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120304Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.Type: ApplicationFiled: November 24, 2022Publication date: April 11, 2024Applicant: Innolux CorporationInventors: Tzu-Sheng Wu, Haw-Kuen Liu, Chung-Jyh Lin, Cheng-Chi Wang, Wen-Hsiang Liao, Te-Hsun Lin
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Patent number: 11939268Abstract: A method of forming low-k material is provided. The method includes providing a plurality of core-shell particles. The core of the core-shell particles has a first ceramic with a low melting point. The shell of the core-shell particles has a second ceramic with a low melting point and a low dielectric constant. The core-shell particles are sintered and molded to form a low-k material. The shell of the core-shell particles is connected to form a network structure of a microcrystal phase.Type: GrantFiled: December 23, 2020Date of Patent: March 26, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuo-Chuang Chiu, Tzu-Yu Liu, Tien-Heng Huang, Tzu-Chi Chou, Cheng-Ting Lin
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Publication number: 20240079348Abstract: An electronic device includes a chip and a circuit structure layer overlapped with the chip. The circuit structure layer includes a redistribution structure layer and an element structure layer, and the redistribution structure layer and the element structure layer are electrically connected to the chip. At least one of the redistribution structure layer and the element structure layer includes at least one opening, and in a normal direction of the electronic device, the at least one opening is overlapped with aside of the chip.Type: ApplicationFiled: August 7, 2023Publication date: March 7, 2024Applicant: InnoLux CorporationInventors: Ker-Yih Kao, Cheng-Chi Wang, Yen-Fu Liu, Ju-Li Wang, Jui-Jen Yueh
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Patent number: 11916077Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.Type: GrantFiled: May 24, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
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Patent number: 8605525Abstract: A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.Type: GrantFiled: November 23, 2010Date of Patent: December 10, 2013Assignee: Macronix International Co., Ltd.Inventors: Yin Chin Huang, Chu Pang Huang, Cheng Chi Liu, Min Kuang Li, Chang Chan Yang, Yi Fang Chang
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Patent number: 8498168Abstract: A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.Type: GrantFiled: April 13, 2011Date of Patent: July 30, 2013Assignee: Macronix International Co., Ltd.Inventors: Yin Chin Huang, Chu Pang Huang, Yi Fang Chang, Cheng Chi Liu, Chang Chan Yang, Min Kuang Lee
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Publication number: 20120263002Abstract: A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.Type: ApplicationFiled: April 13, 2011Publication date: October 18, 2012Inventors: Yin Chin Huang, Chu Pang Huang, Yi Fang Chang, Cheng Chi Liu, Chang Chan Yang, Min Kuang Lee
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Publication number: 20120127797Abstract: A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yin Chin Huang, Chu Pang Huang, Cheng Chi Liu, Min Kuang Li, Chang Chan Yang, Yi Fang Chang
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Patent number: 7580302Abstract: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.Type: GrantFiled: October 23, 2006Date of Patent: August 25, 2009Assignee: Macronix International Co., Ltd.Inventors: Wen Chiao Ho, Chin Hung Chang, Cheng-Chi Liu, Kuen-Long Chang, Chun Hsiung Hung
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Publication number: 20080094891Abstract: A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.Type: ApplicationFiled: October 23, 2006Publication date: April 24, 2008Applicant: Macronix International Co., Ltd.Inventors: Wen-Chiao Ho, Chin-Hung Chang, Cheng-Chi Liu, Kuen-Long Chang, Chun-Hsiung Hung
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Patent number: D921536Type: GrantFiled: November 11, 2019Date of Patent: June 8, 2021Assignee: KWANG YANG MOTOR CO., LTD.Inventors: Ping-Huan Chuang, Chu-Chung Yang, Cheng-Chi Liu
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Patent number: D976756Type: GrantFiled: March 8, 2021Date of Patent: January 31, 2023Assignee: KWANG YANG MOTOR CO., LTD.Inventors: Chia-Sheng Chen, Chu-Chung Yang, Cheng-Chi Liu