Patents by Inventor Cheng-Chi Wu

Cheng-Chi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152679
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Patent number: 11914941
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Patent number: 11100272
    Abstract: A method includes obtaining a layout of a circuit pattern implemented on a semiconductor wafer, and identifying one or more polygons in the layout based on a length criteria. One or more measurement gauges are placed on the identified polygons to thereby obtain measured polygons. A scanning electron microscope (SEM) image of the circuit pattern is obtained. The SEM image is aligned with the layout including the measured polygons. A critical dimension of one or more objects in the SEM image is measured. The one or more objects correspond to the one or more polygons. Based on the measured critical dimension, it is determined whether the circuit pattern is acceptable.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chi Wu, Wen-Chuan Wang
  • Publication number: 20210240906
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Patent number: 11010529
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Publication number: 20210081509
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Publication number: 20200143099
    Abstract: A method includes obtaining a layout of a circuit pattern implemented on a semiconductor wafer, and identifying one or more polygons in the layout based on a length criteria. One or more measurement gauges are placed on the identified polygons to thereby obtain measured polygons. A scanning electron microscope (SEM) image of the circuit pattern is obtained. The SEM image is aligned with the layout including the measured polygons. A critical dimension of one or more objects in the SEM image is measured. The one or more objects correspond to the one or more polygons. Based on the measured critical dimension, it is determined whether the circuit pattern is acceptable.
    Type: Application
    Filed: August 15, 2019
    Publication date: May 7, 2020
    Inventors: Cheng-Chi WU, Wen-Chuan WANG
  • Patent number: 9761411
    Abstract: A system and method for maskless direct write lithography are disclosed. The method includes receiving a plurality of pixels that represent an integrated circuit (IC) layout; identifying a first subset of the pixels that are suitable for a first compression method; and identifying a second subset of the pixels that are suitable for a second compression method. The method further includes compressing the first and second subset using the first and second compression method respectively, resulting in compressed data. The method further includes delivering the compressed data to a maskless direct writer for manufacturing a substrate. In embodiments, the first compression method uses a run-length encoding and the second compression method uses a dictionary-based encoding. Due to the hybrid compression method, the compressed data can be decompressed with a data rate expansion ratio sufficient for high-volume IC manufacturing.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: September 12, 2017
    Assignee: Taiwain Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Wu, Jensen Yang, Wen-Chuan Wang, Shy-Jay Lin
  • Patent number: 9658538
    Abstract: A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Yi Liu, Cheng-Chi Wu, Cheng-Hung Chen, Jyuh-Fuh Lin, Wen-Chuan Wang, Shy-Jay Lin
  • Publication number: 20160211117
    Abstract: A system and method for maskless direct write lithography are disclosed. The method includes receiving a plurality of pixels that represent an integrated circuit (IC) layout; identifying a first subset of the pixels that are suitable for a first compression method; and identifying a second subset of the pixels that are suitable for a second compression method. The method further includes compressing the first and second subset using the first and second compression method respectively, resulting in compressed data. The method further includes delivering the compressed data to a maskless direct writer for manufacturing a substrate. In embodiments, the first compression method uses a run-length encoding and the second compression method uses a dictionary-based encoding. Due to the hybrid compression method, the compressed data can be decompressed with a data rate expansion ratio sufficient for high-volume IC manufacturing.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: Cheng-Chi Wu, Jensen Yang, Wen-Chuan Wang, Shy-Jay Lin
  • Publication number: 20160180005
    Abstract: A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Pei-Yi Liu, Cheng-Chi Wu, Cheng-Hung Chen, Jyuh-Fuh Lin, Wen-Chuan Wang, Shy-Jay Lin
  • Publication number: 20140310753
    Abstract: In a method for recording and playing multimedia audiovisual programs using a first television, the first television being is connected to a second television. The first television records a current multimedia audiovisual program being played on the first television in response to a recording command generated according to a user's operation, and sends the recorded multimedia audiovisual program to the second television according to an invoking command received from the second television.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 16, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHENG-CHI WU, KUO-CHIH YU
  • Publication number: 20140098042
    Abstract: A touch panel includes a first substrate, an electronic circuit board, a second substrate, and a number of touch-sensing members arranged on the electronic circuit board. Each of the touch-sensing members comprises a metal dome, an insulating layer covering the metal dome, and a sensing layer formed on the insulating layer. A number of contacting tabs are arranged on the electronic circuit board corresponding to each of the metal domes. The sensing layer generates a first signal in a touch mode when the touch panel is touched by a conductor. The contacting tab generates a second signal in a button mode when the second substrate is deformed when the second substrate is pressed, and the metal dome comes into contact with the contacting tab.
    Type: Application
    Filed: September 26, 2013
    Publication date: April 10, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YAO-CHENG KUO, KUO-CHIH YU, CHENG-CHI WU
  • Publication number: 20110311772
    Abstract: A resin surface layer and a method of fabricating the same, and a composite having the resin surface layer and a method of fabricating the same are provided. The method of fabricating the resin surface layer includes: (a) providing a base, made of a resin and including a plurality of additive particles randomly distributed in the base; (b) changing the orientation of the additive particles to arrange the additive particles in a predetermined form; and (c) drying the base to make a surface of the base exhibit a visual effect of 3D texture. Thus, the visual effect of any 3D texture can be achieved by controlling the orientation of the additive particles.
    Type: Application
    Filed: August 4, 2011
    Publication date: December 22, 2011
    Applicant: SAN FANG CHEMICAL INDUSTRY CO., LTD.
    Inventors: CHUNG-CHIH FENG, PAI-HSIANG WU, CHIEN-CHIA HUANG, CHENG-CHI WU, CHIH-SHIH WANG
  • Publication number: 20110068273
    Abstract: The present invention relates to a radiation-detecting device and an associated detection method. The detection device includes a scintillation crystal and an avalanche photodiode. The surface of the scintillation crystal is coated with a high-reflection layer. When ionizing radiation irradiates the scintillation crystal, the crystal emits luminescence, which passes through or is reflected by the high-reflection layer at least once within the scintillation crystal before it is received by the avalanche photodiode, generating a detection signal.
    Type: Application
    Filed: December 1, 2009
    Publication date: March 24, 2011
    Applicant: NATIONAL YANG MING UNIVERSITY
    Inventors: Fu-Jen KAO, Cheng-Chi WU
  • Publication number: 20100179625
    Abstract: An implantable heating apparatus for a living being of the present invention includes a heating unit, a control unit for controlling operations of the heating unit and an induction driven charge/discharge unit for powering the heating unit. The induction driven charge/discharge unit is composed of a core, a coil set wrapping around the core in at least three axial directions and an energy storing unit for electrically coupling to the coil set. Such that when an external alternate magnetic field is approaching the induction driven charge/discharge unit, the coil set is able to generate induction current that can be stored in the energy storing unit.
    Type: Application
    Filed: April 29, 2009
    Publication date: July 15, 2010
    Applicant: National Yang-Ming University
    Inventors: Fu Jen Kao, Cheng Chun Li, Cheng Chi Wu
  • Publication number: 20100019774
    Abstract: An isolation cell having a test mode, connected between a first block and a second block, wherein the first block can operate in either a power-up mode or a power-down mode, comprises: an input terminal for receiving an input signal that is derived from the first block; an output terminal for outputting an output signal to the second block; a normal-sleep terminal for determining the isolation cell is operated in the power-up mode or in the power-down mode, and the logic level of the normal-sleep terminal is determined by the operation mode of the first block; and, a DFT-sleep terminal is for overwriting the logic level of the normal-sleep terminal when the isolation cell is in the test mode.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 28, 2010
    Applicant: FARADAY TECHNOLOGY CORPORATION
    Inventors: Cheng-Chi WU, Yu-Wen TSAI, Shang-Chih HSIEH, Chun-Sung SU
  • Patent number: 7502282
    Abstract: A digital audio signal player includes a reproducing unit to pick a disc audio signal which is stored in a disk, and a digital signal processor for controlling input and output of the disc audio signal of the memory. Thus, when the system processing unit receives the trigger signal of the trigger switch after the contact member is pressed to contact the trigger switch, the system processing unit drives the digital signal processor to modulate the disc audio signal stored in the memory according to the detected signal of the sensor so as to produce a special audio signal output.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: March 10, 2009
    Assignee: Ya Horng Electronic Co., Ltd.
    Inventor: Cheng-Chi Wu
  • Publication number: 20090061155
    Abstract: A resin surface layer and a method of fabricating the same, and a composite having the resin surface layer and a method of fabricating the same are provided. The method of fabricating the resin surface layer includes: (a) providing a base, made of a resin and including a plurality of additive particles randomly distributed in the base; (b) changing the orientation of the additive particles to arrange the additive particles in a predetermined form; and (c) drying the base to make a surface of the base exhibit a visual effect of 3D texture. Thus, the visual effect of any 3D texture can be achieved by controlling the orientation of the additive particles.
    Type: Application
    Filed: December 19, 2007
    Publication date: March 5, 2009
    Applicant: SAN FANG CHEMICAL INDUSTRY CO., LTD.
    Inventors: Chung-Chih FENG, Pai-Hsiang WU, Chien-Chia HUANG, Cheng-Chi WU, Chih-Shih WANG
  • Publication number: 20080085046
    Abstract: A detailed identification method for articles has an image-taking step and a comparison step. The image-taking step includes acts of using a portable identification device having a close-up lens and a screen to take a detailed image of an undistinguishable article and displaying the detailed image on the screen with an enlarged size. The comparison step includes acts of recalling a detailed image of a legal article from a database and displaying the detailed image on the screen of the portable identification device with an enlarged size. The two detailed images are displayed on the same screen so a user can clearly compare the detailed images to judge whether the undistinguishable article is a fake. The detailed identification method for articles has mobility and can be conveniently and extensively used.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 10, 2008
    Inventors: Yen-Chieh Lee, Raymond R. Chen, Pen-Tsung Huang, Ming-Feng Shih, Jin-Tang Fang, Chung-Min Huang, Cheng-Chi Wu, Minh-Lun Hsieh