Patents by Inventor Cheng-Chia Chiang

Cheng-Chia Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220302257
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20220231066
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chin-Chia Kuo, Wen-Hau Wu, Hua-Mao Chen, Chih-Kung Chang
  • Publication number: 20220216301
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 10163662
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 25, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Publication number: 20180138158
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Shu-Huei Huang
  • Patent number: 9905546
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Huei Huang
  • Publication number: 20170207104
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Application
    Filed: April 4, 2017
    Publication date: July 20, 2017
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Patent number: 9646921
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: May 9, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Publication number: 20160233205
    Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Chia-Kai Shih, Shu-Huei Huang
  • Patent number: 9356008
    Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 31, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Hsin-Ta Lin, Fu-Tang Huang, Yu-Po Wang, Lung-Yuan Wang, Chu-Chi Hsu, Chia-Kai Shih
  • Patent number: 9343421
    Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: May 17, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Chia-Kai Shih, Shu-Huei Huang
  • Patent number: 9343387
    Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 17, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chu-Chi Hsu, Lung-Yuan Wang, Cheng-Chia Chiang, Chia-Kai Shih, Shu-Huei Huang
  • Publication number: 20160020195
    Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.
    Type: Application
    Filed: February 6, 2015
    Publication date: January 21, 2016
    Inventors: Cheng-Chia Chiang, Hsin-Ta Lin, Fu-Tang Huang, Yu-Po Wang, Lung-Yuan Wang, Chu-Chi Hsu, Chia-Kai Shih
  • Publication number: 20150255360
    Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.
    Type: Application
    Filed: August 6, 2014
    Publication date: September 10, 2015
    Inventors: Chu-Chi Hsu, Lung-Yuan Wang, Cheng-Chia Chiang, Chia-Kai Shih, Shu-Huei Huang
  • Publication number: 20150200169
    Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
    Type: Application
    Filed: June 19, 2014
    Publication date: July 16, 2015
    Inventors: Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Chia-Kai Shih, Shu-Huei Huang
  • Publication number: 20150187741
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 2, 2015
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Huei Huang
  • Publication number: 20150187722
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Application
    Filed: April 17, 2014
    Publication date: July 2, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Publication number: 20150123287
    Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 7, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Chu-Chi Hsu, Lung-Yuan Wang, Cheng-Chia Chiang, Chia-Kai Shih
  • Publication number: 20150041972
    Abstract: A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component.
    Type: Application
    Filed: April 10, 2014
    Publication date: February 12, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Kai Shih, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Shih-Hao Tung
  • Patent number: 8802507
    Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 12, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang