Patents by Inventor CHENG-CHIA LIN

CHENG-CHIA LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112957
    Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Xuan Wang, Cheng-Chun Tseng, Yi-Chun Chen, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Publication number: 20240071947
    Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
  • Patent number: 11719880
    Abstract: A perovskite optical element includes a light guiding unit and a luminescent layer. The light guiding unit is configured to conduct light and serves as a resonant cavity. The luminescent layer is a thin film made of perovskite material and clads the light guiding unit. The luminescent layer is configured to be excited by an excitation module to emit light. The light is conducted and output by the light guiding unit. A manufacturing method of a perovskite optical element includes preparing a dip coating solution; dipping a single crystal optical fiber in the dip coating solution for one hour, removing the single crystal optical fiber out of the dip coating solution, and drying the single crystal optical fiber; and placing the single crystal optical fiber into a tube furnace, heating the crystal optical fiber, and introducing synthetic molecules into the tube furnace.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: August 8, 2023
    Assignee: NATIONAL DONG HWA UNIVERSITY
    Inventors: Duc-Huy Nguyen, Jia-Yuan Sun, Chia-Yao Lo, Jia-Ming Liu, Wan-Shao Tsai, Ming-Hung Li, Sin-Jhang Yang, Cheng-Chia Lin, Shien-Der Tzeng, Yuan-Ron Ma, Ming-Yi Lin, Chien-Chih Lai
  • Publication number: 20230118309
    Abstract: A perovskite optical element includes a light guiding unit and a luminescent layer. The light guiding unit is configured to conduct light and serves as a resonant cavity. The luminescent layer is a thin film made of perovskite material and clads the light guiding unit. The luminescent layer is configured to be excited by an excitation module to emit light. The light is conducted and output by the light guiding unit. A manufacturing method of a perovskite optical element includes preparing a dip coating solution; dipping a single crystal optical fiber in the dip coating solution for one hour, removing the single crystal optical fiber out of the dip coating solution, and drying the single crystal optical fiber; and placing the single crystal optical fiber into a tube furnace, heating the crystal optical fiber, and introducing synthetic molecules into the tube furnace.
    Type: Application
    Filed: December 10, 2021
    Publication date: April 20, 2023
    Inventors: DUC-HUY NGUYEN, JIA-YUAN SUN, CHIA-YAO LO, JIA-MING LIU, WAN-SHAO TSAI, MING-HUNG LI, SIN-JHANG YANG, CHENG-CHIA LIN, SHIEN-DER TZENG, YUAN-RON MA, MING-YI LIN, CHIEN-CHIH LAI