Patents by Inventor Cheng-Chia Tsai

Cheng-Chia Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990404
    Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Fong Tsai, Cheng-I Chu, Jyh-Cherng Sheu, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11988553
    Abstract: An optical module is disclosed. The optical module includes a carrier, an optical emitter disposed over the carrier, and a monitor disposed over the carrier and configured to adjust a property of a first light emitted from the optical emitter.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: May 21, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo Sin Huang, Tien-Chia Liu, Ko-Fan Tsai, Cheng-Te Chou, Yan-Te Chou
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Patent number: 11942451
    Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
  • Publication number: 20240094052
    Abstract: An optical module is disclosed. The optical module includes a carrier, an optical emitter disposed over the carrier, and a monitor disposed over the carrier and configured to adjust a property of a first light emitted from the optical emitter.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo Sin HUANG, Tien-Chia LIU, Ko-Fan TSAI, Cheng-Te CHOU, Yan-Te CHOU
  • Publication number: 20240071947
    Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
  • Publication number: 20230368012
    Abstract: The disclosed subject matter provides systems and methods for processing light. An example system can include one or more substrates, and a plurality of meta-units, which are patterned on each of the substrates and configured to modify a phase, an amplitude, or a polarization of the light with a subwavelength resolution. The system can be in a form of a diffractive neural network and be configured to perform target recognition.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 16, 2023
    Applicants: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Nanfang Yu, Cheng-Chia Tsai, Xiaoyan Huang, Zongfu Yu, Zhicheng Wu