Abstract: An electronic device including a hinge module, a first body, a second body, and a flexible display assembled to the first body and the second body is provided. Each of the first body and the second body is pivoted and slidably connected to the hinge module, and a cover of the hinge module is exposed out of the first body and the second body. The first body and the second body are rotated relatively via the hinge module to bend or flatten the flexible display, when the flexible display is bending from a flat state, a bending portion of the flexible display leans against the cover and pushes the cover away from the first body and the second body.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.

Abstract: A manufacturing method of housing structure of electronic device is provided. The manufacturing method includes stacking a first structural layer, a painting layer, and a second structural layer, wherein the painting layer is located between the first and the second structural layers. The layer stacked after the painting layer washes and squeezes at least a portion of the flowing painting layer to form a random texture pattern.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.

Abstract: A water cooling head with sparse and dense fins, including a main body, a first fin set and a second fin set. Wherein a chamber is formed inside the main body, the main body has a first plate and a second plate, the main body forms an inlet channel and an outlet channel, so that the cooling water passes through the chamber. The first fin set and the second fin set are arranged in the chamber, and the first fin set and the second fin set are connected to the first plate respectively. The first fin set comprises several first fins spaced apart, the first fins divide the chamber to form several first channels. The second fin set comprises several second fins spaced apart, the second fins divide the chamber to form several second channels. The water cooling head can increase the overall heat sinking efficiency.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.

Abstract: A portable electronic device including a first body, a second body, a pivot element, a heat source, a first flexible heat conductive element, and a flip cover is provided. The pivot element is connected to the second body, and the second body is pivotally connected to the first body through the pivot element. The heat source is disposed in the first body. The first flexible heat conductive element is thermally coupled to the heat source and extends toward the pivot element from the heat source. The first flexible heat conductive element passes through the pivot element and extends into the inside of the second body and is thus thermally coupled to the second body. The flip cover is pivotally connected to the first body and located on a moving path of the pivot element.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: A display device and a method for operating a display device disclosed herein include transmitting a proximity signal from a proximity sensor, the proximity sensor being positioned under a lower surface of a surface layer with an illumination component being positioned between the surface layer and the proximity sensor, in response to the illumination component being deactivated, receiving a reflected proximity signal based on the proximity signal, determining a proximity value based on the reflected proximity signal and modifying an operation of the display device based on the proximity value. The modifying the operation of the display device includes any one or a combination of activating the illumination component, deactivating the illumination component, or modifying a property of the illumination component.

Abstract: Devices, methods, and systems for detecting proximity. A first light emitter emits light for a first time period while a light detector is not sensing. A second light emitter emits light for a second time period while the light detector is sensing. In some implementations, the first light emitter directly illuminates the light detector during the first time period, whereas the second light emitter is obstructed from directly illuminating the light detector during the second time period. In some implementations, the first light emitter is obstructed from illuminating a display during the first time period, and the second light emitter is obstructed from directly illuminating the light detector during the second time period. In some implementations, the first light emitter emits the light during the first time period such that the light detector maintains a linear responsivity during the second time period.

Abstract: A semiconductor device with different gate structures and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a thermal oxide layer on top and side surfaces of the fin structure, forming a polysilicon structure on the thermal oxide layer, doping portions of the fin structure uncovered by the polysilicon structure to form doped fin portions, forming a nitride layer on the polysilicon structure and the thermal oxide layer, forming an oxide layer on the nitride layer, doping the nitride layer with halogen ions, forming a source/drain region in the fin structure and adjacent to the polysilicon structure, and replacing the polysilicon structure with a gate structure.

Abstract: A display device and a method for operating a display device disclosed herein include transmitting a proximity signal from a proximity sensor, the proximity sensor being positioned under a lower surface of a surface layer with an illumination component being positioned between the surface layer and the proximity sensor, in response to the illumination component being deactivated, receiving a reflected proximity signal based on the proximity signal, determining a proximity value based on the reflected proximity signal and modifying an operation of the display device based on the proximity value.

Abstract: Techniques, devices, and systems disclosed herein include detecting a vertical synchronization (VSYNC) signal cycle, determining a high frequency trigger pulse based on detecting an illumination component's pulse width modulation (PWM) signal, the high frequency trigger pulse corresponding to the illumination component's deactivation times, receiving a delay time period and activating a first sensor, at a first time, within the VSYNC signal cycle, the first time determined based on the high frequency trigger pulse and the delay time period. The first sensor may sense a first sensor reading and may be deactivated after being activated. A display setting may be adjusted based at least on the first sensor reading and the illumination component may be activated after the first sensor is deactivated.

Abstract: A data processing apparatus is provided having branch prediction circuitry, the branch prediction circuitry having a Branch Target Buffer, BTB. A fetch target queue receives entries corresponding to a sequence of instruction addresses, at least one of the sequence having been predicted using the branch prediction circuitry. A fetch engine is provided to fetch instruction addresses taken from a top of the fetch target queue whilst a prefetch engine sends a prefetch probe to an instruction cache. The BTB is to detect a BTB miss when attempting to populate a storage slot of the fetch target queue and the BTB triggers issuance of a BTB miss probe to the memory to fetch at least one instruction from the memory to resolve the BTB miss using branch-prediction based prefetching.

Abstract: Techniques, devices, and systems disclosed herein include detecting a vertical synchronization (VSYNC) signal cycle, determining a high frequency trigger pulse based on detecting an illumination component's pulse width modulation (PWM) signal, the high frequency trigger pulse corresponding to the illumination component's deactivation times, receiving a delay time period and activating a first sensor, at a first time, within the VSYNC signal cycle, the first time determined based on the high frequency trigger pulse and the delay time period. The first sensor may sense a first sensor reading and may be deactivated after being activated. A display setting may be adjusted based at least on the first sensor reading and the illumination component may be activated after the first sensor is deactivated.

Abstract: A data processing apparatus is provided having branch prediction circuitry, the branch prediction circuitry having a Branch Target Buffer, BTB. A fetch target queue receives entries corresponding to a sequence of instruction addresses, at least one of the sequence having been predicted using the branch prediction circuitry. A fetch engine is provided to fetch instruction addresses taken from a top of the fetch target queue whilst a prefetch engine sends a prefetch probe to an instruction cache. The BTB is to detect a BTB miss when attempting to populate a storage slot of the fetch target queue and the BTB triggers issuance of a BTB miss probe to the memory to fetch at least one instruction from the memory to resolve the BTB miss using branch-prediction based prefetching.