Patents by Inventor Cheng Chieh Lee

Cheng Chieh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960332
    Abstract: An electronic device including a hinge module, a first body, a second body, and a flexible display assembled to the first body and the second body is provided. Each of the first body and the second body is pivoted and slidably connected to the hinge module, and a cover of the hinge module is exposed out of the first body and the second body. The first body and the second body are rotated relatively via the hinge module to bend or flatten the flexible display, when the flexible display is bending from a flat state, a bending portion of the flexible display leans against the cover and pushes the cover away from the first body and the second body.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: April 16, 2024
    Assignee: Acer Incorporated
    Inventors: Yi-Ta Huang, Cheng-Nan Ling, Wu-Chen Lee, Wen-Chieh Tai, Kun-You Chuang
  • Patent number: 11935890
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
  • Patent number: 11918882
    Abstract: An interactive exercise apparatus for guiding a user to perform an exercise includes a display device and a detecting device. The display device is configured to display video imagery which shows an instructor image and at least one motion check image. The motion check image corresponds to a predetermined one of a plurality of body parts of the user, which has a motion guide track and a motion achievement evaluation. The detecting device is configured to detect displacement of the body parts. The motion guide track is displayed on a predetermined position of the video imagery with a predetermined track pattern, corresponding to a movement path of the predetermined body part when the user follows movements demonstrated by the instructor image to perform the exercise. The motion achievement evaluation indicates a matching degree determined according to the displacement of the predetermined body part detected by the detecting device.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: Johnson Health Tech Co., Ltd.
    Inventors: Hsin-Huang Chiang, Yu-Chieh Lee, Ning Chuang, Wei-Ting Weng, Cheng-Ho Yeh
  • Patent number: 11916314
    Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: February 27, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 11748098
    Abstract: A processor is provided with a register file comprising a plurality of vector registers, and an execution core coupled to the register file, where the execution core is configured to execute a set of checksum instructions with a first checksum instruction to specify a first vector operand, a second vector operand, and a result vector operand, where the first vector operand is in a first vector register of the plurality of vector registers, the second vector operand is in a second register of the plurality of vector registers, and the result vector operand is to be written to a third vector register of the plurality of vector registers, and to execute the first checksum instruction, the execution core is configured to accumulate bytes from the first vector operand and the second vector operand into a first portion of the result vector operand and add the accumulated bytes from the first vector operand and the second vector operand to a second portion of the result vector operand to generate the second portion
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: September 5, 2023
    Assignee: Apple Inc.
    Inventors: Ali Sazegari, Chris Cheng-Chieh Lee
  • Publication number: 20220357947
    Abstract: A processor is provided with a register file comprising a plurality of vector registers, and an execution core coupled to the register file, where the execution core is configured to execute a set of checksum instructions with a first checksum instruction to specify a first vector operand, a second vector operand, and a result vector operand, where the first vector operand is in a first vector register of the plurality of vector registers, the second vector operand is in a second register of the plurality of vector registers, and the result vector operand is to be written to a third vector register of the plurality of vector registers, and to execute the first checksum instruction, the execution core is configured to accumulate bytes from the first vector operand and the second vector operand into a first portion of the result vector operand and add the accumulated bytes from the first vector operand and the second vector operand to a second portion of the result vector operand to generate the second portion
    Type: Application
    Filed: May 5, 2021
    Publication date: November 10, 2022
    Inventors: Ali Sazegari, Chris Cheng-Chieh Lee
  • Patent number: 10769065
    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 8, 2020
    Assignee: Apple Inc.
    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee
  • Publication number: 20190294541
    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee
  • Patent number: 10424603
    Abstract: A display panel having a notch extending inwardly from its edge and including a plurality of first signal lines having a first extending direction, a plurality of second signal lines having a second extending direction different from the first extension direction, a plurality of pixel units, and a plurality of transmission lines is provided. The pixel units are electrically connected to the first signal lines and the second signal lines. The transmission lines are electrically connected to the first signal lines. Part of the transmission lines includes a first sub-transmission line, a second sub-transmission line and a third sub-transmission line electrically connected to each other. The first sub-transmission line is disposed between the adjacent second signal lines. The second sub-transmission line is disposed between the adjacent first signal lines. The third sub-transmission line overlaps another transmission line in the second extending direction.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 24, 2019
    Assignee: Au Optronics Corporation
    Inventors: Cheng-Chieh Lee, Chao-Chien Chiu
  • Publication number: 20190252411
    Abstract: A display panel having a notch extending inwardly from its edge and including a plurality of first signal lines having a first extending direction, a plurality of second signal lines having a second extending direction different from the first extension direction, a plurality of pixel units, and a plurality of transmission lines is provided. The pixel units are electrically connected to the first signal lines and the second signal lines. The transmission lines are electrically connected to the first signal lines. Part of the transmission lines includes a first sub-transmission line, a second sub-transmission line and a third sub-transmission line electrically connected to each other. The first sub-transmission line is disposed between the adjacent second signal lines. The second sub-transmission line is disposed between the adjacent first signal lines. The third sub-transmission line overlaps another transmission line in the second extending direction.
    Type: Application
    Filed: June 15, 2018
    Publication date: August 15, 2019
    Applicant: Au Optronics Corporation
    Inventors: Cheng-Chieh Lee, Chao-Chien Chiu
  • Patent number: 10331558
    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 25, 2019
    Assignee: Apple Inc.
    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee
  • Publication number: 20190067800
    Abstract: A mobile device with integral radiation shielding includes a body, a rear housing, and a metal induction sheet. The body includes therein a circuit board, an antenna, and a capacitive proximity sensor circuit. The rear housing covers the body. The metal induction sheet is formed directly on the rear housing as a single part. The metal induction sheet doesn't add extra space, enabling the manufacture of very thin mobile device.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 28, 2019
    Inventors: CHENG-CHIEH LEE, CHIH-CHENG CHANG
  • Publication number: 20190034333
    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee
  • Patent number: 9356638
    Abstract: An FM audio receiver can include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a received pilot tone energy. An accurate operation of the receiver, including but not limited to correct decoding of monophonic/stereophonic reception, can be based on the receiver operating with the same rated maximum system deviation (RMSD) as the received signal itself. Aspects of the disclosure describe a system and method of detecting and matching a receiver's RMSD to that of a received signal by demodulating a carrier bearing a an input signal over a first bandwidth, extracting a pilot energy signal from the input signal, and demodulating the carrier bearing the input signal over a second bandwidth if the pilot energy signal is within a pilot energy range for a first predetermined amount of time.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 31, 2016
    Assignee: Marvell International Ltd.
    Inventor: Chris Cheng-Chieh Lee
  • Patent number: 9161145
    Abstract: An audio receiver may include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a difference between a pilot energy signal and a filtered pilot energy signal. The audio receiver includes a filter that filters the pilot energy signal to generate a filtered pilot energy signal, wherein a variable leakage factor associated with the filter is used to minimize a noise level of the filtered pilot energy signal and to reduce a response time of the audio receiver.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 13, 2015
    Assignee: Marvell International Ltd.
    Inventor: Chris Cheng-Chieh Lee
  • Patent number: 9065709
    Abstract: Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: June 23, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Jungwon Lee, Dimitrios-Alexandros Toumpakaris, Hui-Ling Lou, Chris Cheng-Chieh Lee
  • Patent number: 8953809
    Abstract: A system and method for switching a mode of a receiver between a monophonic and stereophonic mode is disclosed. The method can include generating a residual signal indicative of a noise level associated with a pilot energy signal, calculating a residual block energy level of the residual signal over an observation interval, generating a monitor signal based on a number of times the pilot energy signal is less than a pilot energy threshold during the observation interval and switching the mode of the receiver based on the residual block energy level and the monitor signal.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Marvell International Ltd.
    Inventor: Chris Cheng-Chieh Lee
  • Patent number: 8948402
    Abstract: A receiver may estimate a channel condition based on a difference between a pilot energy signal and a filtered pilot energy signal. The receiver may further switch to a stereophonic mode when both the difference and an energy level of the pilot energy signal satisfy a predetermined requirement of the receiver, and switch to a monophonic mode when either the difference or the energy level of the pilot energy signal fail to satisfy the predetermined requirement of the receiver.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 3, 2015
    Assignee: Marvell International Ltd.
    Inventor: Chris Cheng-Chieh Lee
  • Patent number: 8879740
    Abstract: An audio receiver may include a mono/stereo detector that causes the audio receiver to output either a monophonic or a stereophonic signal based on a difference between a pilot energy signal and a filtered pilot energy signal. The audio receiver includes a filter that filters the pilot energy signal to generate a filtered pilot energy signal, wherein a variable leakage factor associated with the filter is used to minimize a noise level of the filtered pilot energy signal and to reduce a response time of the audio receiver.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 4, 2014
    Assignee: Marvell International Ltd.
    Inventor: Chris Cheng-Chieh Lee
  • Patent number: 8792591
    Abstract: Disclosed herein are systems and methods for accurate removal of I/Q mismatch in received signals of an analog FM receiver. The analog FM receiver includes a down-converter, a calibration circuit that estimates I/Q mismatch values, and a compensation circuit that uses the estimated mismatch values to reduce the effects of I/Q mismatch. In one aspect, the calibration circuit uses an adaptive dual-parameter compensation scheme to iteratively correct the received signals by approximating a coefficient value and an amplitude value that minimize the signals' amplitude variation from the amplitude value. In another aspect, phase and amplitude mismatch parameters can be determined using the coefficient value.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: July 29, 2014
    Assignee: Marvell International Ltd.
    Inventor: Chris Cheng-Chieh Lee